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cy7c601xx, cy7c602xx encore? ii low-voltage microcontroller cypress semiconductor corporation ?198 champion court ?san jose, ca 95134-1709 ?408-943-2600 document 38-16016 rev. *j revised june 6, 2011 1. features encore ? ii low-voltage (encore ii lv) ? enhanced component reduction ? internal crystalless oscillator with support for optional external clock or external crystal or resonator ? configurable i/o for real world interface without external components enhanced 8-bit microcontroller ? harvard architecture ? m8c cpu speed up to 12 mhz or sourced by an external crystal, resonator, or clock signal internal memory ? 256 bytes of random access memory (ram) ? 8 kb of flash including electrically erasable read only memory (eerom) emulation low power consumption ? typically 2.25 ma at 3 mhz ? 5 ? a sleep in-system reprogrammability ? enables easy firmware update general-purpose i/o (gpio) ports ? up to 36 gpio pins ? 2-ma source current on all gpio pins ? configurable 8 or 50 ma per pi n current sink on designated pins ? each gpio port supports high-impedance inputs, configurable pull-up, open drain output, complementary metal oxide semiconductor (cmos), and transistor-transistor logic (ttl) inputs, and cmos output ? maskable interrupts on all i/o pins spi serial communication ? master or slave operation ? configurable up to 2 mbit per second transfers ? supports half-duplex single-data line mode for optical sensors 2-channel 8-bit or 1-channel 16 -bit capture timer registers, which store both rising and falling edge times ? two registers each for two input pins ? separate registers for rising and falling edge capture ? simplifies interface to radio frequency (rf) inputs for wireless applications internal low-power wakeup timer during suspend mode ? periodic wakeup with no external components programmable interval timer interrupts reduced rf emissions at 27 mhz and 96 mhz watchdog timer (wdt) low-voltage detection (lvd) with user-selectable threshold voltages improved output drivers to redu ce electromagnetic interference (emi) operating voltage from 2.7 v to 3.6 v dc operating temperature from 0 c to 70 c available in 40-pin plastic dual inline package (pdip), 24-pin small outline integrated circuit (soic), 24-pin quad small outline package (qsop) and shrink small outline package (ssop), 48-pin ssop advanced development tools based on cypress psoc ? tools industry-standard programmer support 2. logic block diagram internal 12 mhz oscillator clock control crystal oscillator cy7c601xx only por / low-voltage detect watchdog timer m8c cpu 16 extended i/o pins 16 gpio pins wakeup timer capture timers 12-bit timer v dd interrupt control 4 spi/gpio pins flash 8 kb ram 256 byte
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 2 of 68 3. contents applications ...................................................................... 3 introduction ....................................................................... 3 conventions ...................................................................... 3 pinouts .............................................................................. 4 pin assignments .......................................................... 5 register summary ............................................................ 7 cpu architecture .............................................................. 9 cpu registers ................................................................... 9 flags register ............................................................. 9 addressing modes ............... ...................................... 11 instruction set summary ............................................... 13 memory organization ..................................................... 15 flash program memory organi zation ....................... 15 data memory organization ....................................... 16 flash .......................................................................... 16 srom ........................................................................ 16 srom function descriptions . ................................... 17 srom table read description ................................. 20 clocking .......................................................................... 22 trim values for the iosctr register ....................... 22 clock architecture description .................................. 23 cpu clock during sleep mode . .............. ........... ....... 30 reset ................................................................................ 31 power on reset ........................................................ 32 watchdog timer reset ........... .............. .............. ....... 32 sleep mode ...................................................................... 32 sleep sequence ........................................................ 33 wakeup sequence ...... .............. .............. ........... ....... 34 low-voltage detect control ......................................... 35 por compare state ................................................. 36 eco trim register .................................................... 36 general-purpose i/o ports ............................................. 37 port data registers ................................................... 37 gpio port configuration ........................................... 38 serial peripheral interface (spi) .................................... 45 spi data register ...................................................... 46 spi configure register ............................................. 46 spi interface pins ...................................................... 48 timer registers .............................................................. 48 registers ................................................................... 48 interrupt controller ......................................................... 55 architectural description ........................................... 56 interrupt processing .................................................. 56 interrupt latency ....................................................... 56 interrupt registers .............. ....................................... 57 absolute maximum ratings .......................................... 60 dc characteristics .................................................... 60 ac characteristics .................................................... 61 ordering information ...................................................... 64 package handling ........................................................... 64 package diagrams .......................................................... 65 document history page ................................................. 67 sales, solutions, and legal information ...................... 68
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 3 of 68 4. applications the cy7c601xx and cy7c602xx are targeted for the following applications: pc wireless human interface devices (hid) ? mice (optomechanical, optical, trackball) ? keyboards ? presenter tools gaming ? joysticks ? gamepad general-purpose wireless applications ? remote controls ? barcode scanners ? pos terminal ? consumer electronics ? to y s 5. introduction the encore ii lv family brings the features and benefits of the encore ii to non-usb applications. the encore ii family has an integrated oscillator that elim inates the external crystal or resonator, reducing overall cost. other external components, such as wakeup circuitry, are also integrated into this chip. the encore ii lv is a low-voltage, low-cost 8-bit flash-programmable microcontroller. the encore ii lv features up to 36 gpio pins. the i/o pins are grouped into five ports (port 0 to 4). the pins on ports 0 and 1 are configured individually, when the pins on ports 2, 3, and 4 are only configured as a group. each gpio port supports high-impedance inputs, configurable pull-up, open-drain output, cmos, and ttl inputs, and cmos output with up to five pins that support programmable drive strength of up to 50-ma sink current. additionally, each i/o pin is used to generate a gpio interrupt to the microcontroller. each gpio port has its own gpio interrupt vector with t he exception of gpio port 0. gpio port 0 has, in addition to the port interrupt vector, three dedicated pins that have independent interr upt vectors (p0.2?p0.4). the encore ii lv features an internal oscillator. optionally, an external 1-mhz to 24-mhz crystal is used to provide a higher precision reference. the encore ii lv also supports external clock. the encore ii lv has 8 kb of flash for user code and 256 bytes of ram for stack space and user variables. in addition, encore ii lv includes a wdt, a vectored interrupt controller, a 16-bit free-running timer with capture registers, and a 12-bit programmable interval timer. the power on reset (por) circuit detects when power is applied to the device, resets the logic to a known state, and execut es instructions at flash address 0x0000. when power falls below a programmable trip voltage, it generates a reset or is configur ed to generate an interrupt. there is a lvd circuit that detects when v cc drops below a programmable trip voltage. this is configurable to generate a lvd interrupt to inform the processor about the low-voltage event. por and lvd share the same interrupt; there is no separate interrupt for each. the wdt en sures the firmware never gets stalled in an infinite loop. the microcontroller supports 17 maskable interrupts in the vectored interrupt controller. all interrupts can be masked. interrupt sources include lvr or por, a programmable interval timer, a nominal 1.024 ms programmable output from the free-running timer, two capture timers, five gpio ports, three gpio pins, two spi, a 16-bit free-running timer wrap, and an internal wakeup timer interrupt. the wakeup timer causes periodic interrupts when enabled. the capture timers interrupt whenever a new timer value is saved due to a selected gpio edge event. a total of eight gpio interrupts support both ttl or cmos thresholds. for additional flexibility, on the edge-sensitive gpio pins, the interrupt polarity is programmable to be either rising or falling. the free-running timer generates an interrupt at 1024- ? s rate. it also generates an interrupt when the free-running counter overflow occurs ? every 16.384 ms. the duration of an event under firmware control is measured by reading the timer at the start and end of an event, then calculating the difference between the two values. the two 8-bit capture timer registers save a programmable 8-bit range of the free-running timer when a gpio edge occurs on the two capture pins (p0.5 and p0.6). the two 8-bit capture registers are ganged into a single 16-bit capture register. the encore ii lv supports in-system programming by using the p1.0 and p1.1 pins as the serial programming mode interface. 6. conventions in this document, bit positions in the registers are shaded to indicate which members of the encore ii lv family implement the bits. available in all encore ii lv family members cy7c601xx only
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 4 of 68 7. pinouts figure 7-1. package configurations 1 2 3 4 5 6 9 11 15 16 17 18 19 20 22 21 nc p0.7 tio1/p0.6 tio0/p0.5 int2/p0.4 int1/p0.3 clkin\p0.0 p2.0 p1.5/smosi p1.3/ssel p3.1 p3.0 v dd p1.2 p1.1 p1.0 14 p1.4/sclk 10 p2.1 nc v ss 12 13 7 8 int0/p0.2 clkout\p0.1 24 23 p1.7 p1.6/smiso 24-pin qsop cy7c60223 top view 1 2 3 4 5 6 9 11 15 16 17 18 19 20 22 21 nc p0.7 tio1/p0.6 tio0/p0.5 int2/p0.4 int1/p0.3 clkin\p0.0 p2.0 p1.6/smiso p3.0 p1.4/sclk p3.1 p1.2 p1.3/ssel v dd p1.1 14 p1.5/smosi 10 p2.1 v ss p1.0 12 13 7 8 int0/p0.2 clkout\p0.1 24 23 nc p1.7 24-pin soic cy7c60223 1 2 3 4 5 6 9 11 v dd p4.1 p2.6 p2.4 10 p2.5 p2.3 12 7 8 p4.0 p2.7 40-pin pdip cy7c60123 13 14 15 16 17 18 p2.2 p2.1 p2.0 p0.7 t1o1/p0.6 tio0/p0.5 int0/p0.2 clkin/p0.0 clkout/p0.1 v ss 19 int2/p0.4 int1/p0.3 21 22 23 24 26 25 p3.0 p1.4/sclk p1.6/smiso p1.5/smosi p1.2 p1.3/ssel v dd p1.1 p1.7 p1.0 28 27 p3.2 p3.1 31 32 33 34 35 36 38 37 p4.2 v ss p4.3 p3.6 p3.7 p3.5 p3.4 30 p3.3 29 40 39 20 1 2 3 4 5 6 9 11 nc nc nc nc v dd p4.1 p2.6 p2.4 10 p2.5 p2.3 12 7 8 p4.0 p2.7 48-pin ssop cy7c60123 13 14 15 16 17 18 21 23 p2.2 p2.1 p2.0 p0.7 tio1/p0.6 tio0/po.5 int0/p0.2 clkin/p0.0 22 clkout/p0.1 v ss 24 19 20 int2/p0.4 int1/p0.3 27 28 29 30 31 32 34 33 p3.0 p1.4/sclk p1.6/smiso p1.5/smosi p1.2 p1.3/ssel v dd p1.1 26 p1.7 p1.0 25 36 35 p3.2 p3.1 39 40 41 42 43 44 46 45 nc p4.2 v ss p4.3 p3.6 p3.7 p3.5 p3.4 38 nc p3.3 37 48 47 nc nc
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 5 of 68 7.1 pin assignments table 7-1. pin assignments 48 ssop 40 pdip 24 qsop 24 soic name description 7 3 ? ? p4.0 gpio port 4?configured as a group (nibble) 62? ?p4.1 42 38 ? ? p4.2 43 39 ? ? p4.3 34 30 19 18 p3.0 gpio port 3?configured as a group (byte) 35 31 20 19 p3.1 36 32 ? ? p3.2 37 33 ? ? p3.3 38 34 ? ? p3.4 39 35 ? ? p3.5 40 36 ? ? p3.6 41 37 ? ? p3.7 15 11 11 11 p2.0 gpio port 2?configured as a group (byte) 14 10 10 10 p2.1 13 9 ? ? p2.2 12 8 ? ? p2.3 11 7 ? ? p2.4 10 6 ? ? p2.5 95? ?p2.6 84? ?p2.7 25 21 14 13 p1.0 gpio port 1 bit 0/issp-sclk if this pin is used as a general-purpose output it draws current. it is, therefore, configured as an input to reduce current draw. 26 22 15 14 p1.1 gpio port 1 bit 1/issp-sdata if this pin is used as a general-purpose output it draws current. it is, therefore, configured as an input to reduce current draw. 28 24 17 16 p1.2 gpio port 1 bit 2 29 25 18 17 p1.3/ssel gpio port 1 bit 3?configured individually alternate function is ssel signal of the spi bus. 30 26 21 20 p1.4/sclk gpio port 1 bit 4?configured individually alternate function is sclk signal of the spi bus. 31 27 22 21 p1.5/smosi gpio port 1 bit 5?configured individually alternate function is smosi signal of the spi bus. 32 28 23 22 p1.6/smiso gpio port 1 bit 6?configured individually alternate function is smiso signal of the spi bus. 33 29 24 23 p1.7 gpio port 1 bit 7?configured individually ttl voltage threshold. 23 19 9 9 p0.0/clkin gpio port 0 bit 0?configured individually on cy7c601xx, optional clock in when extern al oscillator is disabled or external oscillator input when external oscillator is enabled. on cy7c602xx, oscillator input when configured as clock in.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 6 of 68 22 18 8 8 p0.1/clkout gpio port 0 bit 1?configured individually on cy7c601xx, optional clock out when external oscillator is disabled or external oscillator output drive when external oscillator is enabled. on cy7c602xx, oscillator output when configured as clock out. 21 17 7 7 p0.2/int0 gpio port 0 bit 2?configured individually optional rising edge interrupt int0. 20 16 6 6 p0.3/int1 gpio port 0 bit 3?configured individually optional rising edge interrupt int1. 19 15 5 5 p0.4/int2 gpio port 0 bit 4?configured individually optional rising edge interrupt int2. 18 14 4 4 p0.5/tio0 gpio port 0 bit 5?configured individually alternate function timer capture inputs or timer output tio0. 17 13 3 3 p0.6/tio1 gpio port 0 bit 6?configured individually alternate function timer capture inputs or timer output tio1. 16 12 2 2 p0.7 gpio port 0 bit 7?configured individually 1,2,3, 4 ? 1 1 nc no connect 45,46, 47,48 ? 12 24 nc no connect 51 v dd power 27 23 16 15 44 40 ? ? v ss ground 24 20 13 12 table 7-1. pin assignments (continued) 48 ssop 40 pdip 24 qsop 24 soic name description
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 7 of 68 8. register summary table 8-1. encore ii lv register summary the xio bit in the cpu flags register must be set to acce ss the extended register space for all registers above 0xff. addr name 7 6 5 4 3 2 1 0 r/w default 00 p0data p0.7 p0.6/tio1 p0.5/tio0 p0.4/int2 p0.3/int1 p0.2/int0 p0.1/ clkout p0.0/clkin bbbbbbbb 00000000 01 p1data p1.7 p1.6/smiso p1.5/smosi p1.4/sclk p1.3/ssel p1.2 p1.1 p1.0 bbbbbbbb 00000000 02 p2data p2.7?p2.2 p2.1?p2.0 bbbbbbbb 00000000 03 p3data p3.7?p3.2 p3.1?p3.0 bbbbbbbb 00000000 04 p4data reserved p4.3?p4.0 ----bbbb 00000000 05 p00cr reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable -bbbbbbb 00000000 06 p01cr clk output int enable int act low ttl thresh high sink open drain pull-up enable output enable bbbbbbbb 00000000 07?09 p02cr? p04cr reserved int act low ttl thresh reserved open drain pull-up enable output enable --bb-bbb 00000000 0a?0b p05cr? p06cr tio output int enable int act low ttl thresh reserved open drain pull-up enable output enable bbbb-bbb 00000000 0c p07cr reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable -bbb-bbb 00000000 0d p10cr reserved int enable int act low reserved output enable -bb----b 00000000 0e p11cr reserved int enable int act low reserved open drain reserved output enable -bb--b-b 00000000 0f p12cr clk output int enable int act low ttl threshold reserved open drain pull-up enable output enable bbbb-bbb 00000000 10 p13cr reserved int enable int act low reserved high sink open drain pull-up enable output enable -bb-bbbb 00000000 11?13 p14cr? p16cr spi use int enable int act low reserved high sink open drain pull-up enable output enable bbb-bbbb 00000000 14 p17cr reserved int enable int act low reserved high sink open drain pull-up enable output enable -bb-bbbb 00000000 15 p2cr reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable -bbbbbbb 00000000 16 p3cr reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable -bbbbbbb 00000000 17 p4cr reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable -bbb-bbb 00000000 20 frtmrl free-running timer [7:0] bbbbbbbb 00000000 21 frtmrh free-running timer [15:8] bbbbbbbb 00000000 22 tcap0r capture 0 rising [7:0] rrrrrrrr 00000000 23 tcap1r capture 1 rising [7:0] rrrrrrrr 00000000 24 tcap0f capture 0 falling [7:0] rrrrrrrr 00000000 25 tcap1f capture 1 falling [7:0] rrrrrrrr 00000000 26 pitmrl prog interval timer [7:0] rrrrrrrr 00000000 27 pitmrh reserved prog interval timer [11:8] ----rrrr 00000000 28 pirl prog interval [7:0] bbbbbbbb 00000000 29 pirh reserved prog interval [11:8] ----bbbb 00000000 2a tmrcr first edge hold 8-bit capture prescale cap0 16-bit enable reserved bbbbb--- 00000000 2b tcapinte reserved cap1 fall active cap1 rise active cap0 fall active cap0 rise active ----bbbb 00000000 2c tcapints reserved cap1 fall active cap1 rise active cap0 fall active cap0 rise active ----bbbb 00000000 30 cpuclkcr reserved cpu clk select -------b 00000000 31 tmrclkcr tcapclk divider tcapclk select itmrclk divider itmrclk select bbbbbbbb 1000 1111 32 clkiocr reserved xosc select xosc enable eftb disabled clkout select ---bbbbb 00000000
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 8 of 68 note in the r/w column: b = both read and write r = read only w = write only c = read or clear d = calibration value. must not change during normal use 34 iosctr foffset[2:0] gain[4:0] bbbbbbbb 000ddddd 35 xosctr reserved xosc xgm [2:0] reserved mode ---bbb-b 000ddddd 36 lposctr 32 khz low power reserved 32 khz bias trim [1:0] 32 khz freq trim [3:0] b-bbbbbb d-dddddd 3c spidata spidata[7:0] bbbbbbbb 00000000 3d spicr swap lsb first comm mode cpol cpha sclk select bbbbbbbb 00000000 da int_clr0 gpio port 1 sleep timer int1 gpio port 0 spi receive spi transmit int0 por/lvd bbbbbbbb 00000000 db int_clr1 tcap0 prog interval timer 1 ms timer reserved bbb----- 00000000 dc int_clr2 reserved gpio port 4 gpio port 3 gpio port 2 reserved int2 16-bit counter wrap tcap1 -bbb-bbb 00000000 de int_msk3 enswint reserved r------- 00000000 df int_msk2 reserved gpio port 4 int enable gpio port 3 int enable gpio port 2 int enable reserved int2 int enable 16-bit counter wrap int enable tcap1 int enable -bbb-bbb 00000000 e1 int_msk1 tcap0 int enable prog interval timer int enable 1 ms timer int enable reserved bbb----- 00000000 e0 int_msk0 gpio port 1 int enable sleep timer int enable int1 int enable gpio port 0 int enable spi receive int enable spi transmit int enable int0 int enable por/lvd int enable bbbbbbbb 00000000 e2 int_vc pending interrupt [7:0] bbbbbbbb 00000000 e3 reswdt reset watchdog timer [7:0] wwwwwww w 00000000 -- cpu_a temporary register t1 [7:0] -------- 00000000 -- cpu_x x[7:0] -------- 00000000 -- cpu_pcl program counter [7:0] -------- 00000000 -- cpu_pch program counter [15:8] -------- 00000000 -- cpu_sp stack pointer [7:0] -------- 00000000 f7 cpu_f reserved xio super carry zero global ie ---brbbb 00000010 ff cpu_scr gies reserved wdrs pors sleep reserved reserved stop r-ccb--b 00010100 1e0 osc_cr0 reserved no buzz sleep timer [1:0] cpu speed [2:0] --bbbbbb 00001000 1e3 lvdcr reserved porlev[1:0] reserved vm[2:0] --bb-bbb 00000000 1eb eco_tr sleep duty cycle [1:0] reserved bb------ 00000000 1e4 vltcmp reserved lvd ppor ------rr 00000000 table 8-1. encore ii lv register summary (continued) the xio bit in the cpu flags register must be set to acce ss the extended register space for all registers above 0xff. addr name 7 6 5 4 3 2 1 0 r/w default
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 9 of 68 9. cpu architecture this family of microcontrollers is based on a high-performance, 8-bit, harvard-architecture mi croprocessor. five registers control the primary operation of the cpu core. these registers are affected by various instructions, but are not directly accessible through the register space by the user. the 16-bit program counter r egister (cpu_pc) directly addresses the full 8 kb of program memory space. the accumulator register (cpu_a) is the general-purpose register that holds results of inst ructions that specify any of the source addressing modes. the index register (cpu_x) holds an offset value used in the indexed addressing modes. typically, this is used to address a block of data within the data memory space. the stack pointer register (cpu_sp) holds the address of the current top-of-stack in the data memory space. it is affected by the push, pop, lcall, call, reti, and ret instructions, which manage the software stack. it is also affected by the swap and add instructions. the flag register (cpu_f) has three status bits: zero flag bit [1]; carry flag bit [2]; supervisory state bit [3]. the global interrupt enable bit [0] is used to globally enable or disable interrupts. the user cannot manipulate the supervisory state status bit [3]. the flags are affected by arithmetic, logic, and shift operations. the manner in which each flag is changed is dependent upon the instruction being executed (and, or, xor). see table 11-1 on page 13. 10. cpu registers 10.1 flags register the flags register is only set or reset with logical instruction. table 9-1. cpu registers and register name register register name flags cpu_f program counter cpu_pc accumulator cpu_a stack pointer cpu_sp index cpu_x table 10-1. cpu flags register (cpu_f) [r/w] bit # 7 6 5 4 3 2 1 0 field reserved xio super carry zero global ie read/write ? ? ? r/w r r/w r/w r/w default 00000010 bit [7:5]: reserved bit 4: xio set by the user to select between the register banks. 0 = bank 0 1 = bank 1 bit 3: super indicates whether the cpu is executing us er code or supervisor code. (this code ca nnot be accessed directly by the user.) 0 = user code 1 = supervisor code bit 2: carry set by cpu to indicate whether there is a carry in the previous logical or arithmetic operation. 0 = no carry 1 = carry bit 1: zero set by cpu to indicate whether there is a zero resu lt in the previous logical or arithmetic operation. 0 = not equal to zero 1 = equal to zero bit 0: global ie determines whether all interrupts are enabled or disabled. 0 = disabled 1 = enabled note this register is readable with explicit address 0xf7. the or f, expr and and f, expr are used to set and clear the cpu_f bits.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 10 of 68 10.1.1 accumulator register 10.1.2 index register 10.1.3 stack pointer register 10.1.4 cpu program counter high register 10.1.5 cpu program counter low register table 10-2. cpu accumulator register (cpu_a) bit # 7 6 5 4 3 2 1 0 field cpu accumulator [7:0] read/write ???????? default 00000000 bit [7:0]: cpu accumulator [7:0] 8-bit data value holds the result of any logical or arit hmetic instruction that uses a source addressing mode. table 10-3. cpu x register (cpu_x) bit # 7 6 5 4 3 2 1 0 field x [7:0] read/write ???????? default 00000000 bit [7:0]: x [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode. table 10-4. cpu stack pointer register (cpu_sp) bit # 7 6 5 4 3 2 1 0 field stack pointer [7:0] read/write ???????? default 00000000 bit [7:0]: stack pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack. table 10-5. cpu program coun ter high register (cpu_pch) bit # 7 6 5 4 3 2 1 0 field program counter [15:8] read/write ???????? default 00000000 bit [7:0]: program counter [15:8] 8-bit data value holds the higher byte of the program counter. table 10-6. cpu program counter low register (cpu_pcl) bit # 7 6 5 4 3 2 1 0 field program counter [7:0] read/write ???????? default 00000000 bit [7:0]: program counter [7:0] 8-bit data value holds the lower byte of the program counter.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 11 of 68 10.2 addressing modes 10.2.1 source immediate the result of an instruction usin g this addressing mode is placed in the a register, the f register, the sp register, or the x register, which is specified as part of the instruction opcode. operand 1 is an immediate value that serves as a source for the instruction. arithmetic instructions require tw o sources; the se cond source is the a, x, sp, or f register spec ified in the opcode. instructions using this addressing mode are two bytes in length. examples 10.2.2 source direct the result of an instruction usin g this addressing mode is placed in either the a register or the x register, whic h is specified as part of the instruction opc ode. operand 1 is an address that points to a location in either the ram memory space or the register space that is the source for the instru ction. arithmetic instructions require two sources; the second s ource is the a register or x register specified in the opc ode. instructions using this addressing mode are two bytes in length. examples 10.2.3 source indexed the result of an instruction usin g this addressing mode is placed in either the a register or the x r egister, which is specified as part of the instruction opcode. operand 1 is added to the x register forming an address that points to a location in either the ram memory space or the register sp ace that is the source for the instruction. arithmetic instruct ions require two sources; the second source is the a register or x register specified in the opcode. instructions using this addressing mode are two bytes in length. examples 10.2.4 destination direct the result of an instruction usin g this addressing mode is placed within either the ram memory space or the register space. operand 1 is an address that points to the location of the result. the source for the instruction is either the a register or the x register, which is specified as part of the instruction opcode. arithmetic instructions require tw o sources; the second source is the location specified by operand 1. instructions using this addressing mode are two bytes in length. examples table 10-7. source immediate opcode operand 1 instruction immediate value add a, 7 ;in this case, the immediate value of 7 is added with the accumulator and the result is placed in the accumulator. mov x, 8 ;in this case, the immediate value of 8 is moved to the x register. and f, 9 ;in this case, the immediate value of 9 is logically anded with the f register and the result is placed in the f register. table 10-8. source direct opcode operand 1 instruction source address add a, [7] ;in this case, the value in the ram memory location at address 7 is added with the accumulator, and the result is placed in the accumulator. mov x, reg[8] ;in this case, the value in the register space at address 8 is moved to the x register. table 10-9. source indexed opcode operand 1 instruction source index add a, [x+7] ;in this case, the value in the memory location at address x + 7 is added with the accumulator, and the result is placed in the accumulator. mov x, reg[x+8] ;in this case, the value in the register space at address x + 8 is moved to the x register. table 10-10. destination direct opcode operand 1 instruction destination address add [7], a ;in this case, the value in the memory location at address 7 is added with the accumulator, and the result is placed in the memory location at address 7. the accumulator is unchanged. mov reg[8], a ;in this case, the accumulator is moved to the register space location at address 8. the accumulator is unchanged.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 12 of 68 10.2.5 destination indexed the result of an instruction usin g this addressing mode is placed within either the ram memory space or the register space. operand 1 is added to the x regi ster forming the address that points to the location of the resu lt. the source for the instruction is the a register. arithmetic inst ructions require two sources; the second source is the location specified by operand 1 added with the x register. instructions using this addressing mode are two bytes in length. example 10.2.6 destination direct source immediate the result of an instruction usin g this addressing mode is placed within either the ram memory space or the register space. operand 1 is the address of th e result. the source for the instruction is operand 2, which is an immediate value. arithmetic instructions require two source s; the second source is the location specified by operand 1. instructions using this addressing mode are three bytes in length. examples 10.2.7 destination indexed source immediate the result of an instruction usin g this addressing mode is placed within either the ram memory space or the register space. operand 1 is added to the x register to form the address of the result. the source for the instru ction is operand 2, which is an immediate value. arithmetic instru ctions require two sources; the second source is the location specified by operand 1 added with the x register. instructions using this addressing mode are three bytes in length. examples 10.2.8 destination direct source direct the result of an instruction usin g this addressing mode is placed within the ram memory. operand 1 is the address of the result. operand 2 is an address that points to a location in the ram memory that is the source for th e instruction. this addressing mode is only valid on the mov inst ruction. the instruction using this addressing mode is three bytes in length. example table 10-11. destination indexed opcode operand 1 instruction destination index add [x+7], a ;in this case, the value in the memory location at address x+7 is added with the accumulator and the result is placed in the memory location at address x+7. the accumulator is unchanged. table 10-12. destination direct source immediate opcode operand 1 operand 2 instruction destination address immediate value add [7], 5 ;in this case, value in the memory location at address 7 is added to the immediate value of 5, and the result is placed in the memory location at address 7. mov reg[8], 6 ;in this case, the immediate value of 6 is moved into the register space location at address 8. table 10-13. destination indexed source immediate opcode operand 1 operand 2 instruction destination index immediate value add [x+7], 5 ;in this case, the value in the memory location at address x+7 is added with the immediate value of 5, and the result is placed in the memory location at address x+7. mov reg[x+8], 6 ;in this case, the immediate value of 6 is moved into the location in the register space at address x+8. table 10-14. destination direct source direct opcode operand 1 operand 2 instruction destination address source address mov [7], [8] ;in this case, the value in the memory location at address 8 is moved to the memory location at address 7.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 13 of 68 10.2.9 source indirect post increment the result of an instruction usin g this addressing mode is placed in the accumulator. operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the so urce of the instruction. the indirect address is incremented as part of the instruction execution. this addressing mode is only valid on the mvi instruction. the instruction us ing this addressing mode is two bytes in length. refer to the psoc designer: assembly language user guide for further details on mvi instruction. example 10.2.10 destination indirect post increment the result of an instruction usin g this addressing mode is placed within the memory space. operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the dest ination of the instruction. the indirect address is incremented as part of the instruction execution. the source for the inst ruction is the accumulator. this addressing mode is only valid on the mvi instruction. the instruction using this addressing mode is two bytes in length. example 11. instruction set summary the instruction set is summarized in ta b l e 11 - 1 numerically and serves as a quick referenc e. the instruction set summary tables are described in detail in the psoc designer: assembly language user guide . table 10-15. source indirect post increment opcode operand 1 instruction source address mvi a, [8] ;in this case, the value in the memory location at address 8 is an indirect address. the memory location pointed to by the indirect address is moved into the accumulator. the indirect address is then incremented. table 10-16. destination indirect post increment opcode operand 1 instruction destination address mvi [8], a ;in this case, the value in the memory location at address 8 is an indirect address. the accumulator is moved into the memory location pointed to by the indirect address. the indirect address is then incremented. table 11-1. instruction set summary sorted numerically by opcode order opcode hex cycles bytes instruction format [1, 2] flags opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags 00 15 1 ssc 2d 8 2 or [x+expr], a z 5a 5 2 mov [expr], x 01 4 2 add a, expr c, z 2e 9 3 or [expr], expr z 5b 4 1 mov a, x z 02 6 2 add a, [expr] c, z 2f 10 3 or [x+expr], expr z 5c 4 1 mov x, a 03 7 2 add a, [x+expr] c, z 30 9 1 halt 5d 6 2 mov a, reg[expr] z 04 7 2 add [expr], a c, z 31 4 2 xor a, expr z 5e 7 2 mov a, reg[x+expr] z 05 8 2 add [x+expr], a c, z 32 6 2 xor a, [expr] z 5f 10 3 mov [expr], [expr] 06 9 3 add [expr], expr c, z 33 7 2 xor a, [x+expr] z 60 5 2 mov reg[expr], a 07 10 3 add [x+expr], expr c, z 34 7 2 xor [expr], a z 61 6 2 mov reg[x+expr], a 08 4 1 push a 35 8 2 xor [x+expr], a z 62 8 3 mov reg[expr], expr 09 4 2 adc a, expr c, z 36 9 3 xor [expr], expr z 63 9 3 mov reg[x+expr], expr 0a 6 2 adc a, [expr] c, z 37 10 3 xor [x+expr], expr z 64 4 1 asl a c, z 0b 7 2 adc a, [x+expr] c, z 38 5 2 add sp, expr 65 7 2 asl [expr] c, z 0c 7 2 adc [expr], a c, z 39 5 2 cmp a, expr if (a=b) z=1 if (a cy7c601xx, cy7c602xx document 38-16016 rev. *j page 14 of 68 12 6 2 sub a, [expr] c, z 3f 10 2 mvi [ [expr]++ ], a 6c 8 2 rlc [x+expr] c, z 13 7 2 sub a, [x+expr] c, z 40 4 1 nop 6d 4 1 rrc a c, z 14 7 2 sub [expr], a c, z 41 9 3 and reg[expr], expr z 6e 7 2 rrc [expr] c, z 15 8 2 sub [x+expr], a c, z 42 10 3 and reg[x+expr], expr z 6f 8 2 rrc [x+expr] c, z 16 9 3 sub [expr], expr c, z 43 9 3 or reg[expr], expr z 70 4 2 and f, expr c, z 17 10 3 sub [x+expr], expr c, z 44 10 3 or reg[x+expr], expr z 71 4 2 or f, expr c, z 18 5 1 pop a z 45 9 3 xor reg[expr], expr z 72 4 2 xor f, expr c, z 19 4 2 sbb a, expr c, z 46 10 3 xor reg[x+expr], expr z 73 4 1 cpl a z 1a 6 2 sbb a, [expr] c, z 47 8 3 tst [expr], expr z 74 4 1 inc a c, z 1b 7 2 sbb a, [x+expr] c, z 48 9 3 tst [x+expr], expr z 75 4 1 inc x c, z 1c 7 2 sbb [expr], a c, z 49 9 3 tst reg[expr], expr z 76 7 2 inc [expr] c, z 1d 8 2 sbb [x+expr], a c, z 4a 10 3 tst reg[x+expr], expr z 77 8 2 inc [x+expr] c, z 1e 9 3 sbb [expr], expr c, z 4b 5 1 swap a, x z 78 4 1 dec a c, z 1f 10 3 sbb [x+expr], expr c, z 4c 7 2 swap a, [expr] z 79 4 1 dec x c, z 20 5 1 pop x 4d 7 2 swap x, [expr] 7a 7 2 dec [expr] c, z 21 4 2 and a, expr z 4e 5 1 swap a, sp z 7b 8 2 dec [x+expr] c, z 22 6 2 and a, [expr] z 4f 4 1 mov x, sp 7c 13 3 lcall 23 7 2 and a, [x+expr] z 50 4 2 mov a, expr z 7d 7 3 ljmp 24 7 2 and [expr], a z 51 5 2 mov a, [expr] z 7e 10 1 reti c, z 25 8 2 and [x+expr], a z 52 6 2 mov a, [x+expr] z 7f 8 1 ret 26 9 3 and [expr], expr z 53 5 2 mov [expr], a 8x 5 2 jmp 27 10 3 and [x+expr], expr z 54 6 2 mov [x+expr], a 9x 11 2 call 28 11 1 romx z 55 8 3 mov [expr], expr ax 5 2 jz 29 4 2 or a, expr z 56 9 3 mov [x+expr], expr bx 5 2 jnz 2a 6 2 or a, [expr] z 57 4 2 mov x, expr cx 5 2 jc 2b 7 2 or a, [x+expr] z 58 6 2 mov x, [expr] dx 5 2 jnc 2c 7 2 or [expr], a z 59 7 2 mov x, [x+expr] ex 7 2 jacc fx 13 2 index z table 11-1. instruction set summary sorted numerically by opcode order (continued) opcode hex cycles bytes instruction format [1, 2] flags opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 15 of 68 12. memory organization 12.1 flash program memory organization figure 12-1. program memory space with interrupt vector table after reset address 16-bit pc 0x0000 program execution begins here after a reset 0x0004 por/lvd 0x0008 int0 0x000c spi transmitter empty 0x0010 spi receiver full 0x0014 gpio port 0 0x0018 gpio port 1 0x001c int1 0x0020 reserved 0x0024 reserved 0x0028 reserved 0x002c reserved 0x0030 reserved 0x0034 1 ms interval timer 0x0038 programmable interval timer 0x003c timer capture 0 0x0040 timer capture 1 0x0044 16-bit free-running timer wrap 0x0048 int2 0x004c reserved 0x0050 gpio port 2 0x0054 gpio port 3 0x0058 gpio port 4 0x005c reserved 0x0060 reserved 0x0064 sleep timer 0x0068 program memory begins here (if below interrupts not used, program memory can start lower) 0x1fff
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 16 of 68 12.2 data memory organization the cy7c601xx and cy7c602xx microcontrollers provide up to 256 bytes of data ram figure 12-2. data memory organization 12.3 flash this section describes the flash block of encore ii lv. much of the visible flash functionalit y, including programming and security, are implemented in the m8c supervisory read only memory (srom). encore ii lv flash has an endurance of 1000 erase and write cycles and a ten y ear data retention capability. 12.3.1 flash programming and security all flash programming is performed by code in the srom. the registers that control flash prog ramming are only visible to the m8c cpu when it is executing out of srom. this makes it impossible to read, write, or erase the flash by avoiding the security mechanisms implemented in the srom. customer firmware only programs flash through srom calls. the data or code images are sourced through any interface with the appropriate support firmware. this type of programming requires a ?bootloader??a piece of firmware resident on the flash. for safety reasons, this bootloader is not overwritten during firmware rewrites. the flash provides four extra auxiliary rows to hold flash block protection flags, boot time calibration values, configuration tables, and any device values. the routines to access these auxiliary rows are documented in the srom section. the auxiliary rows are not affected by the device erase function. 12.3.2 in-system programming encore ii lv devices enable in-system programming by using the p1.0 and p1.1 pins as the serial programming mode interface. this allows an external controller to make the encore ii lv part enter serial programming mode and then use the test queue to issue flash access functions in the srom. 12.4 srom the srom holds the code to boot the part, calibrate circuitry, and perform flash operations ( ta b l e 1 2 - 1 lists the srom functions). the functions of the srom are accessed in normal user code or operating from flash. the srom exists in a separate memory space from user code. to access srom functions, the supervisory system call (ssc) inst ruction is exec uted, which has an opcode of 00h. before executing ssc, the m8c?s accumulator is loaded with the desired srom function code from ta b l e 1 2 - 1 . undefined functions causes a halt if called from user code. the srom functions execute code with calls; therefore, the functions require stack space. with the exception of reset, all of the srom functi ons have a parameter block in sram that must be configur ed before executing the ssc. ta b l e 12-2 on page 17 lists all possible parameter block variables. the meaning of each parameter, with regard to a specific srom function, is described later in this section. after reset address 8-bit psp 0x00 stack begins here and grows upward top of ram memory 0xff table 12-1. srom function codes function code function name stack space 00h swbootreset 0 01h readblock 7 02h writeblock 10 03h eraseblock 9 05h eraseall 11 06h tableread 3 07h checksum 3
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 17 of 68 two important variables used fo r all functions are key1 and key2. these variables help di scriminate betwe en valid and inadvertent sscs. key1 always has a value of 3ah, while key2 has the same value as the stack pointer when the srom function begins execution. this is the stack pointer value when the ssc opcode is executed, plus three. if either of the keys do not match the expected values, the m8c halts (with the exception of the swbootreset function). the following code puts the correct value in key1 and key2. the code starts with a halt, to force the program to jump direct ly into the setup code and not run into it. halt sscop: mov [key1], 3ah mov x, sp mov a, x add a, 3 mov [key2], a 12.4.1 return codes the srom also features return codes and lockouts. return codes determine the success or failure of a particular function. the return code is stored in key1?s position in the parameter block. the checksum and tableread functions do not have return codes because key1 ?s position in the parameter block is used to return other data. read, write, and erase operations may fail if the target block is read- or write-protected. block protection levels are set during device programming. the eraseall function overwrites data in addition to leaving the entire user flash in the erase state. the eraseall function loops through the number of flash macros in the product, executing the following sequence: erase, bulk pr ogram all zeros, erase. after the user space in all flash macros are erased, a second loop erases and then programs eac h protection block with zeros. 12.5 srom function descriptions 12.5.1 swbootreset function the srom function, swbootre set, is responsible for transitioning the device from a re set state to running user code. the swbootreset function is executed whenever the srom is entered with an m8c accumulator value of 00h: the sram parameter block is not used as an input to the function. this happens, by design, after a hardware reset, because the m8c's accumulator is reset to 00h or when user code executes the ssc instruction with an accumulator value of 00h. the swbootreset function does not execute when the ssc instruction is executed with a bad key value and a non zero function code. an encore ii lv device executes the halt instruction if a bad value is given for either key1 or key2. the swbootreset function verifies the integrity of the calibration data by way of a 16-bit checksum, before releasing the m8c to run user code. 12.5.2 readblock function the readblock function is used to read 64 contiguous bytes from flash: a block. the function first checks the protec tion bits and de termines if the desired blockid is readable. if read protection is turned on, the readblock function exits setting the accumulator and key2 back to 00h. key1 has a value of 01h, indicating a read failure. if read protection is not enabled, the fu nction reads 64 bytes from the flash using a romx instruction and stores the results in sram using an mvi instruction. the firs t of the 64 bytes is stored in sram at the address indicated by the value of the pointer parameter. when the readblo ck completes successfully the accumulator, key1, and key2 all have a value of 00h. table 12-2. srom function parameters variable name sram address key1/counter/return code 0,f8h key2/tmp 0,f9h blockid 0,fah pointer 0,fbh clock 0,fch mode 0,fdh delay 0,feh pcl 0,ffh table 12-3. srom return codes return code description 00h success 01h function not allowed due to level of protection on block 02h software reset without hardware reset 03h fatal error, srom halted table 12-4. readblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executed blockid 0,fah flash block number pointer 0,fbh first of 64 addresses in sram where returned data is stored
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 18 of 68 12.5.3 writeblock function the writeblock function is used to store data in flash. data is moved 64 bytes at a time from sram to flash using this function. the writeblock function first checks the protection bits and determines if the desired blockid is writable. if write protection is turned on, the writeblock function exits setting the accumulator and key2 back to 00h. key1 has a value of 01h, indicating a write failure. the configuration of the writeblock function is straightforward. the blockid of the flash block, where the data is stored, is det ermined and stored at sram address fah. the sram address of the first of the 64 bytes to be stored in flash is indicated using the pointer variable in the parameter block (sram address fbh). finally, the clock and delay value are set correctly. the clock value determines the length of the write pulse used to store the data in flash. the clock and delay values are dependent on the cpu speed and must be set correctly. refer to the clocking section for additional information. 12.5.4 eraseblock function the eraseblock function is used to erase a block of 64 contiguous bytes in flash. th e eraseblock function first checks the protection bits and determi nes if the desired blockid is writable. if write protection is turned on, the eraseblock function exits setting the accumulator and key2 back to 00h. key1 has a value of 01h, indicating a write failure. the eraseblock function is only useful as the first step in programming. erasing a block does not make data in a block fully unreadable. if the objective is to obliterate data in a block, the best method is to perform an eraseblock followed by a writeblock of all zeros. to set up the parameter block fo r eraseblock, correct key values must be stored in key1 and key2. the block number to be erased is stored in the blockid variable and the clock and delay values are set based on the current cpu speed. 12.5.5 protectblock function the encore ii lv devices offer flash protection on a block-by-block basis. table 12-7 lists the protection modes available. in the table, er and ew indicate the ability to perform external reads and writes; iw is used for internal writes. internal reading is always permitted using the romx instruction. the ability to read using the srom readblock function is indicated by sr. the protection level is stored in two bits according to ta b l e 1 2 - 7 . these bits are bit packed into 64 bytes of the protection block. theref ore, each protection block byte stores the protection level for four flash blocks. the bits are packed into a byte, with the lowest numbered block?s protection level stored in the lowest numbered bits in ta b l e 1 2 - 7 . the first address of the protection block contains the protection level for blocks 0 through 3; the second address is for blocks 4 through 7. the 64th byte stores the protection level for blocks 252 through 255. only an eraseall decreases the protection level by placing zeros in all locations of the protection block. to set the level of protection, the protectblock functi on is used. this function takes data from sram, starting at address 80h, and ors it with the current values in the protection block. the result of the or operation is then stored in the protection block. the eraseblock function does not change the protection level for a block. because the sram location for the protection data is fixed and there is only one protection block for every flash macro, the protectblock function expects very few variables in the parameter block to be set before calling the function. the parameter block values that are, besides the keys, are the clock and delay values. table 12-5. writeblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executing block id 0,fah 8 kb flash block number (00h?7fh) 4 kb flash block number (00h?3fh) 3 kb flash block number (00h?2fh) pointer 0,fbh first 64 addresses in sram where the data is stored in flash is located before calling writeblock clock 0,fch clock divider used to set the write pulse width delay 0,feh for a cpu speed of 12 mhz set to 56h table 12-6. eraseblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executed blockid 0,fah flash block number (00h?7fh) clock 0,fch clock divider used to set the erase pulse width delay 0,feh for a cpu speed of 12 mhz set to 56h table 12-7. protection modes mode settings description marketing 00b sr er ew iw unprotected unprotected 01b sr er ew iw read protect factory upgrade 10b sr er ew iw disable external write field upgrade 11b sr er ew iw disable internal write full protection 76543210 block n+3 block n+2 block n+1 block n
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 19 of 68 12.5.6 eraseall function the eraseall function performs a seri es of steps that destroy the user data in the flash macros and resets the protection block in each flash macro to all zero s (the unprotected state). the eraseall function does not affe ct the three hidden blocks above the protection block in each flash macro. the first of these four hidden blocks is used to store th e protection table for its 8 kb of user data. the eraseall function begins by erasing the user space of the flash macro with the highest address range. a bulk program of all zeros is then performed on the same flash macro, to destroy all traces of previous contents. the bulk program is followed by a second erase that leaves the fl ash macro ready for writing. the erase, program, erase sequenc e is then performed on the next lowest flash macro in the address space if it exists. following erase of the user space, the prot ection block for the flash macro with the highest address range is erased. following erase of the protection block, zeros are written into every bit of the protection table. the next lowest flash ma cro in the address space then has its protection block erased and filled with zeros. the result of the eraseall function is that all user data in flash is destroyed and the flash is left in an unprogrammed state, ready to accept one of the various wr ite commands. the protection bits for all user data are also reset to the zero state. besides the keys, the clock and delay parameter block values are also set. 12.5.7 tableread function the tableread function gives the user access to part specific data stored in the flash during manufacturing. it also returns a revision id for the die (not to be confused with the silicon id). the table space for the encore ii lv is simply a 64-byte row broken up into eight tables of eight bytes (see figure 12-3 on page 21). the tables are numbered zero through seven. all user and hidden blocks in the cy7c601xx/cy7c602xx parts consist of 64 bytes. an internal table (table 0) holds the silicon id and returns the revision id. the silicon id is returned in sram, while the revision and family ids are returned in the cpu_a and cpu_x registers. the silicon id is a value placed in the table by programming the flash and is controlled by cypress semiconductor product engineering. the revision id is hard coded into the srom and also redundantly placed in srom table 1. this is discussed in detail later in this section. srom table 1 holds family/die id and revision id values for the device and returns a one-byte internal revision counter. the internal revision counter starts with a value of zero and is incremented when one of the ot her revision numbers is not incremented. it is reset to zero when one of the other revision numbers is incremented. the internal revision count is returned in the cpu_a register. the cpu_x register is always set to ffh when table 1 is read. the cpu_a and cpu_x registers always return a value of ffh when tables 2 to 7 are read. the blockid value, in the parameter block, indicates which table must be returned to the user. only the three least significant bits of the blockid parameter are used by tableread function for encore ii lv devices. the upper five bits are ignored. when the function is called, it transfers bytes from the table to sram addresses f8h?ffh. the m8c?s a and x registers are used by the tableread function to return the die?s revision id. the revision id is a 16-bit value hard coded into the srom that uniquely identifies the die?s design. the return values for the corresponding table calls are tabulated as shown in table 12-11 . table 12-11. return values for table read table 12-8. protectblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed clock 0,fch clock divider used to set the write pulse width delay 0,feh for a cpu speed of 12 mhz set to 56h table 12-9. eraseall parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed clock 0,fch clock divider us ed to set the write pulse width delay 0,feh for a cpu speed of 12 mhz set to 56h table 12-10. table read parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed. blockid 0,fah table number to read. table number return value a x 0 revision id family id 1 internal revision counter 0xff 2-7 0xff 0xff
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 20 of 68 12.6 srom table read description the silicon ids for encore ii lv devices are stored in the srom tables in the part, as shown in figure 12-3 on page 21. the silicon id can be read out from the pa rt using srom table reads. this is demons trated in the following pseudo code. as ment ioned in the section srom on page 16, the srom variables occupy address f8h th rough ffh in the sram. each of the variables and their definitions are given in the section srom on page 16. area sscparmblka(ram,abs) org f8h // variables are defined starting at address f8h ssc_key1: ; f8h supervisory key ssc_returncode: blk 1 ; f8h result code ssc_key2 : blk 1 ;f9h supervisory stack ptr key ssc_blockid: blk 1 ; fah block id ssc_pointer: blk 1 ; fbh pointer to data buffer ssc_clock: blk 1 ; fch clock ssc_mode: blk 1 ; fdh clockw clocke multiplier ssc_delay: blk 1 ; feh flash macro sequence delay count ssc_write_resultcode: blk 1 ; ffh temporary result code _main: mov a, 2 mov [ssc_blockid], a// to read from table 2 - trim values for the imo are stored in table 2 mov x, sp ; copy sp into x mov a, x ; a temp stored in x add a, 3 ; create 3 byte stack frame (2 + pushed a) mov [ssc_key2], a ; save stack frame for supervisory code ; load the supervisory code for flash operations mov [ssc_key1], 3ah ;flash_oper_key - 3ah mov a,6 ; load a with specific operation. 06h is the code for table (read table 12-1 on page 16) ssc ; ssc call the supervisory rom // at the end of the ssc command the silicon id is stored in f8 (msb) and f9(lsb) of the sram .terminate: jmp .terminate
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 21 of 68 figure 12-3. srom table 12.6.1 checksum function the checksum function calculates a 16-bit checksum over a user-specifiable number of blocks, within a single flash macro (bank) starting from block zero. the blockid parameter is used to pass in the number of bl ocks to calculate the checksum over. a blockid value of ?1? ca lculates the checksum of only block 0, while a blockid value of ?0? calculates the checksum of all 256 user blocks. the 16-bit checksum is returned in key1 and key2. the parameter key1 hold s the lower eight bits of the checksum and the parameter key2 holds the upper eight bits of the checksum. the checksum algorithm executes the followi ng sequence of three instructions over the nu mber of blocks times 64 to be checksummed. romx add [key1], a adc [key2], 0 va l id o p er at i ng reg i o n f8h f9h fah fbh fch fdh feh ffh table 0 table 1 table 2 table 3 table 4 table 5 table 6 table 7 silicon id [15-8] silicon id [7-0] 24 mhz iosctr at 3.30v 24 mhz iosctr at 3.00v 24 mhz iosctr at 2.85v 24 mhz iosctr at 2.70v 32 khz lposctr at 3.30v 32 khz lposctr at 3.00v 32 khz lposctr at 2.85v 32 khz lposctr at 2.70v family / die id revision id table 12-1. checksum parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed blockid 0,fah number of flash blocks to calculate checksum on
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 22 of 68 13. clocking the encore ii lv has two internal oscillators, the internal 24-mhz oscillator and the 32-khz low-power oscillator. the internal 24-mhz oscillator is designed such that it is trimmed to an output frequency of 24 mh z over temperature and voltage variation. the internal 24-mhz oscillator accuracy is 24 mhz ?22% to +10% (between 0 and 70c). no external components are required to achieve this level of accuracy. firmware is responsible for selecting the correct trim values from the user row to match the power supply voltage in the end application and writing the values to the trim registers iosctr and lposctr. the internal low-speed oscillator (ilo) of nominally 32 khz provides a slow clock source for the encore ii lv in suspend mode. this is used to generate a periodic wakeup interrupt and provide a clock to sequential logic during power-up and power-down events when the main clock is stopped. in addition, this oscillator can be used as a clocking source for the interval timer clock (itmrclk) and capture timer clock (tcapclk). the 32-khz low-power oscillator can operate in low-power mode or provide a more accurate clock in normal mode. the internal 32 khz low-power oscillator accuracy ranges from ?53.12% to +56.25%. the 32-khz low-power oscillator can be calibrated against the internal 24-mhz oscillator or another timing source, if desired. encore ii lv provides the ability to load new trim values for the 24-mhz oscillator based on voltage. this allows v dd to be monitored and have firmware trim the oscillator based on the voltage present. the iosctr register is used to set trim values for the 24-mhz oscillator. encore ii lv is initialized with 3.30-v trim values at power-on, then firmware is responsible for transferring the correct set of trim values to the trim registers to match the application?s actual v dd . the 32-khz oscillator generally does not require trim adjustments for voltage but trim values for 32 khz are also stored in supervisory rom. to improve the accuracy of the im o, new trim values are loaded based on supply voltage to the part. for this, firmware needs to make modifications to two registers: 1. the internal oscillator trim register at location 0x34. 2. the gain register at location 0x38. 13.1 trim values for the iosctr register the trim values are stored in srom tables in the part as shown in figure 12-3 on page 21. the trim values are read out from the part based on voltage settings and written to the iosctr register at location 0x34. the following pseudo code shows how this is done. _main: mov a, 2 mov [ssc_blockid], a call srom operation to read the srom table (refer to the section srom table read description on page 20). //after this command is executed, the trim //values for 3.3, 3.0, 2.85 and 2.7 are stored //at locations fc through ff in the ram. srom //calls are explained in the previous section of //this data sheet ; mov a, [fch] // trim values for 3.3 v mov a, [fdh] // trim values for 3.0 v ; mov a, [feh] // trim values for 2.85 v ; mov a, [ffh] // trim values for 2.70 v mov reg[iosctr],a // loading iosctr with // trim values for // 3.0 v .terminate: jmp .terminate gain value for the register at location [0x38]: 3.3 v = 0x40 3.0 v = 0x40 2.85 v = 0xff 2.70 v = 0xff load register [0x38] with the gain values corresponding to the appropriate voltage. table 13-1. oscillator trim values versus voltage settings supervisory rom table function table2 fch 24 mhz iosctr at 3.30 v table2 fdh 24 mhz iosctr at 3.00 v table2 feh 24 mhz iosctr at 2.85 v table2 ffh 24 mhz iosctr at 2.70 v table3 f8h 32 khz lposctr at 3.30 v table3 f9h 32 khz lposctr at 3.00 v
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 23 of 68 when using the 32-khz oscillator, the pitmrl/h is read until two consecutive readings match before sending and receiving data. the following firmware example assumes the developer is interested in the lower byte of the pit. read_pit_counter: mov a, reg[pitmrl] mov [57h], a mov a, reg[pitmrl] mov [58h],a mov [59h], a mov a, reg[pitmrl] mov [60h], a ;;;start comparison mov a,[60h] mov x, [59h] sub a, [59h] jz done mov a, [59h] mov x, [58h] sub a, [58h] jz done mov x, [57h] ;;;correct data is in memory location 57h done: mov [57h], x ret the cy7c601xx part is optionally sourced from an external crystal oscillator. the external clock driving on clkin range is from 187 khz to 24 mhz. 13.2 clock architecture description the encore ii lv clock selection circuitry allo ws the selection of independent clocks for the cpu, interval timers, and capture timers. on the cy7c601xx, the external oscillator is sourced by the crystal oscillator. when the crystal oscillator is disabled, it is sourced directly from the clkin pin. the external crystal oscillator is fed through the eftb block, which is optionally bypassed. 13.2.1 cpu clock the cpu clock, cpuclk, is sourced from the external crystal oscillator, the internal 24-mhz oscillator, or the internal 32-khz low-power oscillator. the selected clock source can optionally be divided by 2 n-1 where n is 0?7 (see table 13-2 on page 25). when it is not being used by the external crystal oscillator, the clkout pin is driven from one of the many sources. this is used for test and also in some applications. the sources that drive the clkout are: clkin after the optional eftb filter internal 24-mhz oscillator internal 32-khz oscillator cpuclk after the programmable divider
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 24 of 68 figure 13-1. cpu clock block diagram scale (divide by 2 n, n = 0-5,7) mux clk_ext clk_24mhz cpuclk sel clk_cpu doubler clk_hs lp osc 32-khz clk_32khz xtal osc 1-24mhz cy7c601xx only mux crystal oscillator disabled xosc sel en clk_ext eftb p0.0 clkin p0.1 clkout cy7c601xx only table 13-1. cpu clock configuration (cpuclkcr) [0x30] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved cpuclk select read/write ? ? ? ? ? ? ? r/w default 0 0 0 0 0 0 0 0 bit [7:1]: reserved bit 0: cpu clk select 0 = internal 24-mhz oscillator 1 = external oscillator source note the cpu speed selection is config ured using the osc_cr0 register ( table 13-2 on page 25).
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 25 of 68 table 13-2. osc control 0 (osc_cr0) [0x1e0] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved no buzz sleep timer [1:0] cpu speed [2:0] read/write ? ? r/w r/w r/w r/w r/w r/w default 0 0 0 0 1 0 0 0 bit [7:6]: reserved bit 5: no buzz during sleep (the sleep bit is set in the cpu_scr register? table 14-1 on page 31), the lvd and por detection circuit is turned on periodically to detect any por and lvd events on the v cc pin (the sleep duty cycle bits in th e eco_tr are used to control the duty cycle? table 16-3 on page 36). to facilitate the detection of por and lvd events, the ?no buzz? bit is used to continuously enable the lvd and por detection circuit during sleep. this results in a faster response to an lvd or por event during sleep at the ex pense of a slightly higher than average sleep current. obtaining the absolute lowest power usage in sleep mode requires the ?no buzz? bit to be clear. 0 = the lvd and por detection circuit is turned on periodically as configured in the sleep duty cycle. 1 = the sleep duty cycle value is overridden. the lvd and por detection circuit is always enabled. note the periodic sleep duty cycle enabling is independent with t he sleep interval shown in the sleep [1:0] bits below. bit [4:3]: sleep timer [1:0] note sleep intervals are approximate. bit [2:0]: cpu speed [2:0] the encore ii lv operates over a range of cpu clock speeds. the reset value for the cpu speed bits is zero; therefore, the defa ult cpu speed is 3 mhz. note this register exists in the second bank of i/o space. th is requires setting the xio bi t in the cpu flags register. sleep timer [1:0] sleep timer clock frequency (nominal) sleep period (nominal) watchdog period (nominal) 00 512 hz 1.95 ms 6 ms 01 64 hz 15.6 ms 47 ms 10 8 hz 125 ms 375 ms 11 1 hz 1 sec 3 sec cpu speed [2:0] cpu when internal oscillator is selected external clock 000 3 mhz (default) clock in/8 001 6 mhz clock in/4 010 12 mhz clock in/2 011 reserved reserved 100 1.5 mhz clock in/16 101 750 khz clock in/32 110 187 khz clock in/128 111 reserved reserved
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 26 of 68 13.2.2 interval timer clock (itmrclk) the itmrclk is sourced from the external crystal oscillator, internal 24-mhz oscillator, internal 32-khz low-power oscillator, or the timer capture clock. a prog rammable prescaler of 1, 2, 3, or 4 then divides the selected source. the 12-bit programmable interval timer is a simple down counter with a programmable reload value. it provides a 1- ? s resolution by default. when the down counter reaches zero, the next clock is spent reloading. the reload value is read and written when the counter is running, but ensure that the counter does not unintentionally reload when the 12-bit reload value is only partially stored between two writes of the 12-bit value. the programmable interval timer generates an interrupt to the cpu on each reload. the parameters to be set show up on the device editor view of psoc designer when you place the encore ii lv timer user module. the parameters are pitimer_source and pitimer_divider. the pitimer_sour ce is the clock to the timer and the pitimer_divider is the value the clock is divided by. the interval register (pitmr) holds the value that is loaded into the pit counter on terminal count. the programmable interval timer resolution is configurable. for example: tcapclk divide by x of cpu clock (for example tcapclk divide by 2 of a 24 mhz cpu clock gives a frequency of 12 mhz) itmrclk divide by x of tcapclk (for example, itmrclk divide by 3 of tcapclk is 4 mhz so resolution is 0.25 ? s). table 13-3. clock i/o configuration (clkiocr) [0x32] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved xosc select xosc enable eftb disabled clkout select read/write ? ? ? r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:5]: reserved bit 4: xosc select this bit, when set, sele cts the external crystal oscillator clock as clock s ource of external clock. when selecting the crystal oscillator clock, first enable the crystal oscillator and wait for few cycles. this is the oscillat or stabilization period. the n select the crystal clock as clock source. similarly, to deselect cryst al clock, first deselect crystal clock as clock source then disa ble the crystal oscillator. 0 = not select external crystal oscillator clock. 1 = select the external crystal oscillator clock. bit 3: xosc enable this bit is only available on the cy7c601xx. this bit when set enables the external crystal oscillator. the external crystal oscillator shares pads clkin and clkout with two gpios?p0.0 and p0.1 respectively. when the external cr ystal oscillator is enabled, the clkin signal comes from the external crystal oscillator block and the output enables on the gpios for p0.0 and p0.1 are disabled, eliminating the possibili ty of contention. when the external crystal oscillator is disabled, the source for clkin signal come s from the p0.0 gpio input. 0 = disable the external oscillator. 1 = enable the external oscillator. note the external crystal oscillator startup time takes up to 2 ms. bit 2: eftb disabled this bit is only available on the cy7c601xx. 0 = enable the eftb filter. 1 = disable the eftb filter, causi ng clkin to bypass the eftb filter. bit [1:0]: clkout select 0 0 = internal 24-mhz oscillator 0 1 = external oscillator source 1 0 = internal 32-khz low-power oscillator 1 1 = cpuclk
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 27 of 68 figure 13-2. programmable interval timer block diagram 13.2.3 timer capture clock (tcapclk) the tcapclk is sourced from the external crystal oscillator, th e internal 24-mhz oscillator or the internal 32-khz low-power oscillator. a programmable prescaler of 2, 4, 6, or 8 then divides the selected source. figure 13-3. timer capture block diagram 12-bit reload value 12-bit down counter 12-bit reload control clock timer configuration status and control system clock interrupt controller 16-bit counter configuration status and control prescale mux capture registers interrupt controller 1ms timer overflow interrupt captimer clock system clock capture0 int capture1 int
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 28 of 68 table 13-1. timer clock configuration (tmrclkcr) [0x31] [r/w] bit # 7 6 5 4 3 2 1 0 field tcapclk divider tcapclk select itmrclk divider itmrclk select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 1 1 1 1 bit [7:6]: tcapclk divider [1:0] tcapclk divider controls the tcapclk divisor. 0 0 = divider value 2 0 1 = divider value 4 1 0 = divider value 6 1 1 = divider value 8 bit [5:4]: tcapclk select the tcapclk select field controls the source of the tcapclk. 0 0 = internal 24-mhz oscillator 0 1 = external crystal oscillator?external crystal oscillator on clkin and clkout if the external crystal oscillator is enabled , clkin input if the external crystal osc illator is disabled (the xosc enable bit of the clkiocr register is cleared? table 13-3 on page 26.) 1 0 = internal 32-khz oscillator 1 1 = tcapclk disabled note the 1024 ? s interval timer is based on the assumption that tcapc lk is running at 4 mhz. changes in tcapclk frequency cause a corresponding change in the 1024 ? s interval timer frequency. bit [3:2]: itmrclk divider itmrclk divider controls the itmrclk divisor. 0 0 = divider value of 1 0 1 = divider value of 2 1 0 = divider value of 3 1 1 = divider value of 4 bit [1:0]: itmrclk select 0 0 = internal 24-mhz oscillator 0 1 = external crystal oscillator?external crystal oscillator on cl kin and clkout if the external crystal oscillator is enabled , clkin input if the external crystal oscillator is disabled. 1 0 = internal 32-khz oscillator 1 1 = tcapclk note changing the source of tmrclk requires both the source and de stination clocks to be running. it is not possible to change the clock source away from tcapclk after that clock is stopped.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 29 of 68 13.2.4 internal clock trim 13.2.5 external clock trim table 13-2. iosc trim (iosctr) [0x34] [r/w] bit # 7 6 5 4 3 2 1 0 field foffset[2:0] gain[4:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 d d d d d the iosc calibrate register is used to calibrate the internal oscillator. the reset value is und efined, but during boot the sro m writes a calibration value that is determi ned during manufacturing test. the ?d? indica tes that the default value is trimmed to 24 mhz at 3.30 v at power on. bit [7:5]: foffset [2:0] this value is used to trim the frequency of the internal oscill ator. these bits are not used in factory calibration and is zero . setting each of these bits causes the appropriate fine offset in oscillator frequency. foffset bit 0 = 7.5 khz foffset bit 1 = 15 khz foffset bit 2 = 30 khz bit [4:0]: gain [4:0] the effective frequency change of the offset input is controlled through the gain input. a lower value of the gain setting incr eases the gain of the offset input. this value sets the size of ea ch offset step for the internal oscillator. nominal gain change (khz/offsetstep) at each bit, typical conditions (24 mhz operation): gain bit 0 = ?1.5 khz gain bit 1 = ?3.0 khz gain bit 2 = ?6 khz gain bit 3 = ?12 khz gain bit 4 = ?24 khz table 13-3. xosc trim (xosctr) [0x35] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved xosc xgm [2:0] reserved mode read/write ? ? ? r/w r/w r/w ? r/w default 0 0 0 d d d ? d this register is used to calibrate the external crystal oscill ator. the reset value is undefined , but during boot the srom writ es a calibration value that is determined during manufacturing test. this is the meaning of ?d? in the default field. bit [7:5]: reserved bit [4:2]: xosc xgm [2:0] amplifier transconductance setting. the xg m settings are recommended for resonators with frequencies of interest for the encore ii lv as below: bit 1: reserved bit 0: mode 0 = oscillator mode 1 = fixed maximum bias test mode resonator xgm setting worst case r (ohms) 6 mhz crystal 001 403 12 mhz crystal 011 201 reserved 111 - 6 mhz ceramic 001 70.4 12 mhz ceramic 011 41
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 30 of 68 13.2.6 lposc trim 13.3 cpu clock during sleep mode when the cpu enters sleep mode the cpuclk select (bit 0, table 13-1 on page 24) is forced to the internal oscillator, and the oscillator is stopped. when the cpu comes out of sleep mode it r uns on the internal oscillator. the internal oscillator recover y time is three clock cycles of the inter nal 32-khz low-power oscillator. if the system requires the cpu to run off the external clock afte r waking from sleep mode, firmware needs to switch the clock s ource for the cpu. if the external clock source is the external osc illator and the oscillator is disabled, firmware needs to enable t he external oscillator, wait for it to stabilize, and then change the clock source. table 13-4. lposc trim (lposctr) [0x36] [r/w] bit # 7 6 5 4 3 2 1 0 field 32 khz low power reserved 32 khz bias trim [1:0] 32 khz freq trim [3:0] read/write r/w ? r/w r/w r/w r/w r/w r/w default 0 ? d d dd d d this register is used to calibrate the 32-khz low-speed oscill ator. the reset value is undefined but during boot the srom write s a calibration value that is determined durin g manufacturing test. this is the meaning of ?d? in the default field. the trim val ue is adjusted vs. voltage as noted in table 13-1 on page 24. bit 7: 32 khz low-power 0 = the 32-khz low-speed oscillator operates in normal mode. 1 = the 32-khz low-speed oscillator operates in a low-power mode . the oscillator continues to function normally but with reduce d accuracy. bit 6: reserved bit [5:4]: 32 khz bias trim [1:0] these bits control the bias current of the low power oscillator. 0 0 = mid bias 0 1 = high bias 1 0 = reserved 1 1 = reserved note do not program the 32-khz bias trim [1:0] field with the rese rved 10b value as the oscillator does not oscillate at all corner conditions with this setting. bit [3:0]: 32-khz freq trim [3:0] these bits are used to trim the frequency of the low-power oscillator.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 31 of 68 14. reset the microcontroller supports two types of resets: por and watchd og reset (wdr). when reset is initiated, all registers are rest ored to their default states and all interrupts are disabled. the occurrence of a reset is recorded in the system status and cont rol register (cpu_scr). bits within this register record the occurrence of por and wdr reset respectively. the firmware interrogates these bits to determine the cause of a reset. the microcontroller resumes execution from flash address 0x0000 after a reset. the internal clocking mode is active after a res et, until changed by user firmware. note the cpu clock defaults to 3 mhz (an internal 24-mhz oscillator divide-by-8 mode) at por to guarantee operation at the low v cc that might be present during the supply ramp. note 3. c = clear. this bit can only be cleared by the user and cannot be set by firmware. table 14-1. system status and control register (cpu_scr) [0xff] [r/w] bit # 7 6 5 4 3 2 1 0 field gies reserved wdrs pors sleep reserved reserved stop read/write r ? r/c [3] r/c [3] r/w ? ? r/w default 0 0 0 1 01 0 0 the bits of the cpu_scr register are used to convey status and control of events for various func tions of an encore ii lv device . bit 7: gies the global interrupt enable status bit is a read only status bit and its use is discouraged. the gies bit is a legacy bit, whic h was used to provide the ability to read the gie bit of the cpu_ f register. however, the cpu_f register is now readable. when this bit is set, it indicates that the gie bit in the cpu_f register is also set which, in turn, i ndicates that the microproces sor services interrupts. 0 = global interrupts disabled 1 = global interrupt enabled bit 6: reserved bit 5: wdrs the wdrs bit is set by the cpu to indicate that a wdr event ha s occurred. the user can read th is bit to determine the type of reset that has occurred. the user can clear but not set this bit. 0 = no wdr 1 = a wdr event has occurred bit 4: pors the pors bit is set by the cpu to indica te that a por event has occurred. the user can read this bit to determine the type of reset that has occurred. the user can clear but not set this bit. 0 = no por 1 = a por event has occurred. (note that wdr event s does not occur until this bit is cleared.) bit 3: sleep set by the user to enable cpu sleep state. cpu remains in sle ep mode until any interrupt is pending. the sleep bit is covered in more detail in the sleep mode section. 0 = normal operation 1 = sleep bit [2:1]: reserved bit 0: stop this bit is set by the user to halt the cpu. the cpu remains ha lted until a reset (wdr, por, or external reset) takes place. if an application wants to stop code execution until a reset, the preferred method is to use the halt instruction rather than writ ing to this bit. 0 = normal cpu operation 1 = cpu is halted (not recommended)
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 32 of 68 14.1 power on reset por occurs every time the power to the device is switched on. por is released when the supply is typically 2.6 v for the upward supply transition, with typically 50 mv of hysteresis during the power on transient. bi t 4 of the system status and control register (cpu_scr) is set to record this event (the register contents are set to 00010000 by the por). after a por, the microprocessor is held off for approximately 20 ms for the v cc supply to stabilize before executing the first instruction at address 0x00 in flash. if the v cc voltage drops below the por downward supply trip point, por is reasserted. the v cc supply needs to ramp linearly from 0 to v cc in less than 200 ms. note the pors status bit is set at por and is only cleared by the user; it cannot be set by firmware. 14.2 watchdog timer reset the user has the option to enable the wdt. the wdt is enabled by clearing the pors bit. when the pors bit is cleared, the wdt cannot be disabled. the only exception to this is if a por event takes place, which disables the wdt. the sleep timer is used to generate the sleep time period and the watchdog time period. the sleep timer uses the internal 32-khz low-power oscillator system clock to produce the sleep time period. the user programs the sleep time period using the sleep timer bits of the osc_cr0 register ( table 13-2 on page 25). when the sleep time elapses (sleep timer overflows), an interrupt to the sleep timer interrupt vector is generated. the watchdog timer period is automatically set to be three counts of the sleep timer overflow. this represents between two and three sleep intervals depending on the count in the sleep timer at the previous wdt clear. when this timer reaches three, a wdr is generated. the user either clears the wdt, or the wdt and the sleep timer. whenever the user writes to the reset wdt register (res_wdt), the wdt is cleared. if the data written is the hex value 0x38, the sleep timer is also cleared at the same time. 15. sleep mode the cpu is put to sleep only by the firmware. this is accomplished by setting the sleep bit in the system status and control register (cpu_scr). this stops the cpu from executing instructions, and the cpu remains asleep until an interrupt is pending, or there is a reset event (either a por or a wdt reset). the low-voltage detection (lvd) circuit drops into fully functional power reduced states, and the latency for the lvd is increased. the actual latency is traded against power consumption by changing sleep duty cycle fiel d of the eco_tr register. the internal 32-khz low-speed oscillator remains running. before entering the suspend mode, firmware optionally configures the 32-khz low-speed oscillator to operate in a low-power mode to help reduce the overall power consumption (using the 32-khz low-power bit, as shown in table 13-4 on page 30). this helps to save approximately 5 ? a; however, the trade off is that the 32-khz low-speed oscillator is less accurate (?53.12% to +56.25% deviation). all interrupts remain active. only the occurrence of an interrupt wakes the part from sleep. the st op bit in the system status and control register (cpu_scr) is cleared for a part to resume out of sleep. the global interrupt enable bit of the cpu flags register (cpu_f) does not have any effect. any unmasked interrupt wakes the system. as a result, any interrupt not intended for waking is disabled through the interrupt mask registers. when the cpu enters sleep mode the cpuclk select (bit 1, table 13-1 on page 24) is forced to the internal oscillator. the internal oscillator recovery time is three clock cycles of the internal 32-khz low-power oscillator. the internal 24-mhz oscillator restarts immediately on exiting sleep mode. if the external crystal oscillator is used, the firmware needs to switch the clock source for the cpu. unlike the internal 24-mhz oscillator, the external oscillator is not automatically shut down during sleep. systems that need the external oscillator disabled in sleep mode must disable the external oscillator bef ore entering sleep mo de. in systems where the cpu runs off the external oscillator, the firmware needs to switch the cpu to the internal oscillator before disabling the external oscillator. on exiting sleep mode, after the clock is stable and the delay time has expired, the instruction immediately following the sleep instruction is executed before the interrupt service routine (if enabled). the sleep interrupt allows the microcontroller to wake up periodically and poll system com ponents while maintaining very low average power consumption. the sleep interrupt is also used to provide periodic interrupts during non-sleep modes. table 14-2. reset watchdog timer (reswdt) [0xe3] [w] bit # 7 6 5 4 3 2 1 0 field reset watchdog timer [7:0] read/write w w w w ww w w default 0 0 0 0 00 0 0 any write to this register clears the watchdog ti mer, a write of 0x38 also clears the sleep timer. bit [7:0]: reset watchdog timer [7:0]
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 33 of 68 15.1 sleep sequence the sleep bit is an input into the sleep logic circuit. this circuit is designed to sequence the device in and out of the hardware sleep state. the hardware sequence to put the device to sleep is shown in figure 15-1 and is defined as follows. 1. firmware sets the sleep bit in the cpu_scr0 register. the bus request (brq) signal to the cpu is immediately asserted. this is a request by the system to halt cpu operation at an instruction boundary. the cpu samples brq on the positive edge of cpuclk. 2. due to the specific timing of t he register write, the cpu issues a bus request acknowledge (bra) on the following positive edge of the cpu clock. the sleep logic waits for the following negative edge of the cpu clock and then asserts a system wide power down (pd) signal. in figure 15-1 the cpu is halted and the system wide power down signal is asserted. 3. the system wide pd signal controls several major circuit blocks: the flash memory mo dule, the internal 24-mhz oscillator, the eftb filter, and the bandgap voltage reference. these circuits transition into a zero power state. the only operational circuits on chip are the low-power oscillator, the bandgap refresh circuit, and the supply voltage monitor (por/lvd) circuit. the external crystal oscillator on encore ii lv devices is not automatically powered down when the cpu enters the sleep state. firmware must explicitly disable the external crystal oscillator to reduce power to levels specified. 15.1.1 low-power in sleep mode to achieve the lowest possible power consumption during suspend or sleep, the following conditions are observed in addition to considerations for the sleep timer and external crystal oscillator: all gpios are set to outputs and driven low clear p11cr[0], p10cr[0] set p10cr[1] make sure the 32-khz oscillator clock is not selected as clock source to itmrclk, tcapclk, and not even as clock output source onto p01_clkout pin. all the other bl ocks go to the power-down mode automati cally on suspend. the following steps are user-configurable and help in reducing the average suspend mode power consumption. 1. configure the power supply monitor at a large regular intervals, control register bi ts are 1,eb[7:6] (power system sleep duty cycle pssdc[1:0]). 2. configure the low-power oscillator into low power mode, control register bit is lopsctr[7]. for low-power considerations during sleep when external clock is used as the cpuclk source, the clock source must be held low to avoid unintentional leakage current. if the clock is held high, then there may be a leakage through m8c. to avoid current consumption make sure itmrclk and tcpclk are not sourced by either low-power 32-khz oscillator or 24-mhz crystal-less oscillator. do not select the 24-mhz or 32-khz oscillator clocks on to the p01_clkout pin. figure 15-1. sleep timing firmware write to scr sleep bit causes an immediate brq iow sleep brq pd bra cpuclk cpu captures brq on next cpuclk edge cpu responds with a bra on the falling edge of cpuclk, pd is asserted. the 24/48 mhz system clock is halted; the flash and bandgap are powered down
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 34 of 68 15.2 wakeup sequence when asleep, the only event t hat wakes the system up is an interrupt. the global interrupt enable of the cpu flag register need not be set. any unmasked interrupt wakes the system up. it is optional for the cpu to actually take the interrupt after the wakeup sequence. the wakeup s equence is synchronized to the 32-khz clock. this is done to sequence a startup delay and allow the flash memory module enough time to power up before the cpu asserts the first read access. another reason for the delay is to enable the oscillator, bandgap, and lvd and por circuits time to settle before actually being used in the system. as shown in figure 15-2 , the wakeup sequence is as follows: 1. the wakeup interrupt occurs and is synchronized by the negative edge of the 32-khz clock. 2. at the following positive edge of the 32-khz cl ock, the system wide pd signal is negated. the flash memory module, internal oscillator, eftb, and bandgap circuit are all powered up to a normal operating state. 3. at the following positive edge of the 32-khz clock, the current values for the precision por and lvd have settled and are sampled. 4. at the following negative edge of the 32-khz clock (after about 15 s nominal), the brq signal is negated by the sleep logic circuit. on the following cpuclk, bra is negated by the cpu and instruction execution resumes. note that in figure 15-2 fixed function blocks, such as fl ash, internal oscillator, eftb, and bandgap, have about 15 s start-up. the wakeup times (interrupt to cpu operational) range from 75 s to 105 s. figure 15-2. wakeup timing int sleep pd bandgap clk32k sample sample lvd/ por cpuclk/ 24mhz bra brq enable cpu (not to scale) sleep timer or gpio interrupt occurs interrupt is double sampled by 32k clock and pd is negated to system cpu is restarted after 90ms (nominal)
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 35 of 68 16. low-voltage detect control table 16-1. low-voltage control register (lvdcr) [0x1e3] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved porlev[1:0] reserved vm[2:0] read/write ? ? r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the configuration of the por and lvd circuit. this register is accessed only in the second bank of i/o space. this requires setting the xio bit in the cpu flags register. bit [7:6]: reserved bit [5:4]: porlev[1:0] this field controls the level below which the precisio n power on-reset (ppor) detector generates a reset. 0 0 = 2.7 v range (trip near 2.6 v) 0 1 = 3 v range (trip near 2.9 v) 1 0 = reserved 1 1 = ppor does not generate a reset, but values read from the voltage monitor comparators register ( table 16-2 on page 36) give the internal ppor comparator state with trip point set to the 3-v range setting. bit 3: reserved bit [2:0]: vm[2:0] this field controls the level below which the low-voltage-detec t trips?possibly generating an interrupt and the level at which flash is enabled for operation. note this register exists in the second bank of i/o space. th is requires setting the xio bit in the cpu flags register. vm[2:0] lvd trip point (v) min max typical 000 2.69 2.72 2.7 001 2.90 2.94 2.92 010 3.00 3.04 3.02 011 3.10 3.15 3.13 100 reserved 101 reserved 110 reserved 111 reserved
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 36 of 68 16.1 por compare state 16.2 eco trim register table 16-2. voltage monitor comparators register (vltcmp) [0x1e4] [r] bit # 7 6 5 4 3 2 1 0 field reserved lvd ppor read/write ? ? ? ? ?? r r default 0 0 0 0 00 0 0 this read-only register allows reading the current state of the lvd and ppor comparators. bit [7:2]: reserved bit 1: lvd this bit is set to indicate that the lvd comparator has tripped, indicating that the supply voltage has gone below the trip poi nt set by vm[2:0] (see table 16-1 on page 35). 0 = no low-voltage-detect event 1 = a low-voltage-detect has tripped bit 0: ppor this bit is set to indicate that the ppor comparator has tripped, indicating that the supply voltage is below the trip point se t by porlev[1:0]. 0 = no ppor event 1 = a ppor event has occurred note this register exists in the second bank of i/o space. th is requires setting the xio bit in the cpu flags register. table 16-3. eco (eco_tr) [0x1eb] [r/w] bit # 7 6 5 4 3 2 1 0 field sleep duty cycle [1:0] reserved read/write r/w r/w ? ? ? ? ? ? default 0 0 0 0 00 0 0 this register controls the ratios (in numbers of 32 khz clock periods) of ?on? time versus ?off? time for lvd and por detection circuit. bit [7:6]: sleep duty cycle [1:0] 0 0 = 1/128 periods of the internal 32 khz low speed oscillator. 0 1 = 1/512 periods of the internal 32 khz low speed oscillator. 1 0 = 1/32 periods of the internal 32 khz low speed oscillator. 1 1 = 1/8 periods of the internal 32 khz low speed oscillator. note this register is only accessed in the second bank of i/o space. this requires setting the xio bit in the cpu flags register.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 37 of 68 17. general-purpose i/o ports 17.1 port data registers 17.1.1 p0 data 17.1.2 p1 data table 17-1. p0 data register (p0data)[0x00] [r/w] bit # 7 6 5 4 3 2 1 0 field p0.7 p0.6/tio1 p0.5/tio0 p0.4/int2 p0.3/int1 p0.2/int0 p0.1/clkout p0.0/clkin read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this register contains the data for port 0. writing to this register sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 0 pins. bit 7: p0.7 data bit [6:5]: p0.6?p0.5 data/tio1 and tio0 beside their use as the p0.6?p0.5 gpios, these pins are also us ed for alternate functions as the capture timer input or timer output pins (tio1 and tio0). to configure the p0.5 and p0.6 pins, refer to the p0.5/tio0?p0.6/tio1 configuration register ( table 17-4 on page 41). bit [4:2]: p0.4?p0.2 data/int2?int0 beside their use as the p0.4?p0.2 gpios, these pins are also us ed for the alternate functions as the interrupt pins (int0?int2) . to configure the p0.4?p0.2 pins, refer to the p0.2/int0?p0.4/int2 configuration register ( table 17-3 on page 40). bit 1: p0.1/clkout beside its use as the p0.1 gpio, this pin is also used for the alternate function as the clk out pin. to configure the p0.1 pin , refer to the p0.1/clkout configuration register ( table 17-2 on page 40). bit 0: p0.0/clkin beside its use as the p0.0 gpio, this pin is also used for the alternate function as the clkin pin. to configure the p0.0 pin, refer to the p0.0/clkin configuration register ( table 17-1 on page 39). table 17-2. p1 data regist er (p1data) [0x01] [r/w] bit # 7 6 5 4 3 2 1 0 field p1.7 p1.6/smiso p1.5/smosi p1.4/sclk p1.3/ssel p1.2 p1.1 p1.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 1. writing to this register sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 1 pins. bit 7: p1.7 data bit [6:3]: p1.6?p1.3 data/spi pins (smiso, smosi, sclk, ssel) beside their use as the p1.6?p1.3 gpios, these pins are also used for the alternate function as the spi interface pins. to configure the p1.6?p1.3 pins, refer to the p1.3?p1.6 configuration register ( table 17-9 on page 42). bit [2:0]: p1.2?p1.0
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 38 of 68 17.1.3 p2 data 17.1.4 p3 data 17.1.5 p4 data 17.2 gpio port configuration all gpio configuration registers have common configuration controls. by default all gpios are configured as inputs. to prevent the inputs from floating, pull-up resistors are enabled. firmware configures each of the gpios before use. the following are bit definitions of the gpio configuration registers. 17.2.1 int enable when set, the int enable bit allows the gpio to generate interrupts. interrupt generate occurs regardless of whether the pin is configured for input or output. all interrupts are edge-sensitive. however, for interrupts that are shared by multiple sources (ports 2, 3, and 4), all inputs are deasserted before a new interrupt occurs. when clear, the corresponding interrupt is disabled on the pin. it is possible to configure gpios as outputs, enable the interrupt on the pin, and then generate the interrupt by driving the appropriate pin state. this is useful in test and may find value in applications too. 17.2.2 int act low when clear, the corresponding interrupt is active high. when set, the interrupt is active low. for p0.2?p0.4 int act low makes interrupts active on the rising edge. int act low set makes interrupts active on the falling edge. 17.2.3 ttl thresh when set, the input has ttl threshold. when clear, the input has standard cmos threshold. note the gpios default to cmos threshold. the user?s firmware must configure the threshold to ttl mode if necessary. table 17-3. p2 data regist er (p2data) [0x02] [r/w] bit # 7 6 5 4 3 2 1 0 field p2.7?p2.2 p2.1?p2.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 000 this register contains the data for port 2. writing to this register sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 2 pins. bit [7:2]: p2 data [7:2] bit [1:0]: p2 data [1:0] table 17-4. p3 data regist er (p3data) [0x03] [r/w] bit # 7 6 5 4 3 2 1 0 field p3.7?p3.2 p3.1?p3.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 000 this register contains the data for port 3. writing to this register sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 3 pins. bit [7:2]: p3 data [7:2] bit [1:0]: p3 data [1:0] table 17-5. p4 data regist er (p4data) [0x04] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved p4.3?p4.0 read/write ???? r/w r/w r/w r/w default 0000 0 0 0 0 this register contains the data for port 4. writing to this register sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 2 pins. bit [7:4]: reserved bit [3:0]: p4 data [3:0] p4.3?p4.0 only exist in the cy7c601xx.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 39 of 68 17.2.4 high sink when set, the output sinks up to 50 ma. when clear, the output sinks up to 8 ma. on the cy7c601xx, only the p3.7, p2.7, p0.1, and p0.0 have a 50 ma sink drive capability. other pins have a 8-ma sink drive capability. on the cy7c602xx, only the p1.7?p1.3 have a 50-ma sink drive capability. other pins have an 8-ma sink drive capability. 17.2.5 open drain when set, the output on the pin is determined by the port data register. if the corresponding bit in the port data register is set, the pin is in high-impedance state; if it is clear, the pin is driven low. when clear, the output is driven low or high. 17.2.6 pull-up enable when set the pin has a 7 k pull-up to v dd . when clear, the pull-up is disabled. 17.2.7 output enable when set, the output driver of the pin is enabled. when clear, the output driver of the pin is disabled. for pins with shared functions there are some special cases. p0.0(clkin) and p0.1(clkout) are not output-enabled when the crystal oscillator is enabled. output enables for these pins are overridden by xosc enable. 17.2.8 spi use the p1.3(ssel), p1.4(sclk), p1 .5(smosi), and p1.6(smiso) pins are used for their dedicated functions or for gpio. to enable the pin for gpio, clear the corresponding spi use bit. the spi function controls the output enable for its dedicated function pins when their gpio enable bit is clear. figure 17-1. gpio block diagram 17.2.9 p0.0/clkin configuration v cc vreg v cc vreg gpio pin r up data out v cc gnd vreg gnd 3.3v drive pull-up enable output enable open drain port data high sink data in ttl threshold table 17-1. p0.0/clkin configuration (p00cr) [0x05] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this pin is shared between the p0.0 gpio use and the clkin pin for the external crys tal oscillator. when the external oscillato r is enabled the settings of this register are ignored. the alternate function of the pin as the clkin is only availabl e in the cy7c601xx. when the external oscillator is enabled (the xosc enable bit of the clkiocr register is set? table 13-3 on page 26), the gpio function of the pin is disabled. the 50-ma sink drive capability is only available in the cy7c601 xx. in the cy7c602xx, only an 8-ma sink drive capability is available on this pin regardless of the setting of the high sink bit.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 40 of 68 17.2.10 p0.1/clkout configuration 17.2.11 p0.2/int0?p0.4/int2 configuration table 17-2. p0.1/clkout configuration (p01cr) [0x06] r/w] bit # 7 6 5 4 3 2 1 0 field clk output int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this pin is shared between the p0.1 gpio use and the clkout pi n for the external crystal oscillator. when the external oscillat or is enabled the settings of this register are ignored. when clk ou tput is set, the internally selected clock is sent out onto p0.1clkout pin. the alternate function of the pin as the cl kout is only available in the cy7c601xx. when the external oscillator is enabled (the xosc enable bit of the clkiocr register is set? table 13-3 on page 26), the gpio function of the pin is disabled. the 50 ma sink drive capability is only available in the cy7c601xx. in the cy7c602xx, only 8 ma sink drive capability is availa ble on this pin regardless of the setting of the high sink bit. bit 7: clk output 0 = the clock output is disabled. 1 = the clock selected by the clk select field (bit [1:0] of the clkiocr register? table 13-3 on page 26) is driven out to the pin. table 17-3. p0.2/int0?p0.4/int2 configuration (p02cr?p04cr) [0x07?0x09] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int act low ttl thresh reserved open drain pull-up enable output enable read/write ? ? r/w r/w ? r/w r/w r/w default 0 0 0 0 00 0 0 these registers control the operation of pins p0.2?p0.4 respectively. these pins are shared between the p0.2?p0.4 gpios and the int0?int2. the int0?int2 interrupts are different from all ot her gpio interrupts. these pins are connected directly to the interrupt controller to provide three edge- sensitive interrupts with independent interrupt vectors. these interrupts occur on a rising edge when int act low is clear and on a falling edge when in t act low is set. these pins are enabled as interrupt source s in the interrupt controller registers ( table 20-7 on page 59 and table 20-5 on page 58). to use these pins as interrupt inputs, configure them as inputs by clearing the corresponding output enable. if the int0?int2 pins are configured as outputs with interrupts enabled, firmware generates an interrupt by writing the appropriate value to the p0.2, p0.3, and p0.4 data bits in the p0 data register. regardless of whether the pins are used as interrupt or gpio pi ns, the int enable, int act low, ttl threshold, open drain, and pull-up enable bits control the behavior of the pin. the p0.2/int0?p0.4/int2 pins are individually configured with the p02cr (0x07), p03cr (0x08), and p04cr (0x09) respectively. note changing the state of the int act low bit generates an unintentional interrupt. when configuring these interrupt sources, follow this procedure: 1. disable interrupt source 2. configure interrupt source 3. clear any pending interrupts from the source 4. enable interrupt source
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 41 of 68 17.2.12 p0.5/tio0?p0.6/tio1 configuration 17.2.13 p0.7 configuration 17.2.14 p1.0 configuration table 17-4. p0.5/tio0?p0.6 /tio1 configuration (p05cr? p06cr) [0x0a?0x0b] [r/w] bit # 7 6 5 4 3 2 1 0 field tio output int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write r/w r/w r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 these registers control the operation of pins p0.5 through p0.6 respectively. p0.5 and p0.6 are shared with tio0 and tio1 respectively. to us e these pins as capture timer inputs, configure them as inputs by clearing the corresponding output enable. to use tio0 and tio1 as timer outputs, set the tiox output and output enable bits. if these pins are configured as outputs and the tio output bit is clear, the firmware controls the tio0 and tio1 inputs b y writing the value to the p0.5 and p0.6 data bits in the p0 data register. regardless of whether either pin is used as a tio or gpio pin the int enable, int act low, ttl threshold, open drain, and pull- up enable control the behavior of the pin. tio0(p0.5) when enabled outputs a positive pulse from the 1024 ? s interval timer. this is the same signal that is used internally to generate the 1024 ? s timer interrupt. this signal is not gated by the inte rrupt enable state. the pulse is active for one cycle of the capture timer clock. tio1(p0.6) when enabled outputs a positive pulse from the progra mmable interval timer. this is the same signal that is used internally to generate the programmable timer interval interrupt. this signal is not gated by the interrupt enable state.the pu lse is active for one cycle of the interval timer clock. the p0.5/tio0 and p0.6/tio1 pins are individually configur ed with the p05cr (0x0a) and p06cr (0x0b), respectively. table 17-5. p0.7 configuration (p07cr) [0x0c] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write ? r/w r/w r/w ? r/w r/w r/w default 00000000 this register controls the operation of pin p0.7. table 17-6. p1.0 configuration (p10cr) [0x0d] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reserved p1.0 and p1.1 pull-up enable output enable read/write r/w r/w r/w ? ?? ? r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.0 pin. bit1: p1.0 and p1.1 pull-up enable 0 = disable the p1.0 and p1.1 pull-up resistors. 1 = enable the internal pull-up resistors for both the p1.0 and p1.1. each of the p1.0 and p1.1 pins is pulled up with r up1 (see dc characteristics on page 60). note there is no 2 ma sourcing capability on this pin. the pin can only sink 5 ma at v ol3 (see dc characteristics on page 60) the p1.0 is an open drain only output. it actively drives a signal low, but cannot actively drive a signal high. if this pin is used as a general purpose output, it draws current . it is therefore configured as an input to reduce current dra w.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 42 of 68 17.2.15 p1.1 configuration 17.2.16 p1.2 configuration 17.2.17 p1.3 co nfiguration (ssel) table 17-7. p1.1 configur ation (p11cr) [0x0e] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reser ved open drain reserved output enable read/write ? r/w r/w ? ?r/w? r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.1 pin. the pull-up resistor on this pin is enabled by the p10cr register. note there is no 2 ma sourcing capability on this pin. the pin can only sink 5 ma at v ol3 (see dc characteristics on page 60) if this pin is used as a general purpose output, it draws current . it is, therefore, configured as an input to reduce current d raw. table 17-8. p1.2 configuration (p12cr) [0x0f] [r/w] bit # 7 6 5 4 3 2 1 0 field clk output int enable int act low ttl threshold reserved open drain pull-up enable output enable read/write r/w r/w r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.2. bit 7: clk output 0 = the internally selected clock is not sent out onto p1.2 pin. 1 = this clk output is used to observe connected external crystal oscillator clock connected in cy7c601xx. when clk output is set, the internally selected clock is sent out onto p1.2 pin. note: table 13-3 on page 26 is used to select the external or internal clock in encore ii devices table 17-9. p1.3 configuration (p13cr) [0x10] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reserved high sink open drain pull-up enable output enable read/write ? r/w r/w ?r/wr/w r/w r/w default 0 0 0 000 0 0 this register controls the operation of the p1.3 pin. this register exists in all encore ii lvparts. the p1.3 gpio?s threshold is always set to ttl. when the spi hardware is enabled or disabled, the pin is controlled by the output enable bit and the corresponding bit in the p1 data register. regardless of whether the pin is used as an spi or gpio pin the int enable, int act low, high sink, open drain, and pull-up ena ble control the behavior of the pin.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 43 of 68 17.2.18 p1.4?p1.6 configurat ion (sclk, smosi, smiso) 17.2.19 p1.7 configuration 17.2.20 p2 configuration table 17-10. p1.4?p1.6 configuration (p14cr?p16cr) [0x11?0x13] [r/w] bit # 7 6 5 4 3 2 1 0 field spi use int enable int act low reserved high sink open drain pull-up enable output enable read/write r/w r/w r/w ?r/wr/w r/w r/w default 0 0 0 000 0 0 these registers control the operation of pins p1.4?p1.6, respectively. these registers exist in all encore ii lv parts. bit 7: spi use 0 = disable the spi alternate function. the pin is used as a gpio 1 = enable the spi function. the spi circuitry controls the output of the pin the p1.4?p1.6 gpio?s threshold is always set to ttl. when the spi hardware is enabled, pins that are configured as spi use have their output enable and output state controlled by the spi circuitry. when the spi hardware is disabled or a pin has its spi use bit clear, the pin is controlled by the output en able bit and the corresponding bit in the p1 data register. regardless of whether any pin is used as an spi or gpio pin the int enable, int act low, high sink, open drain, and pull-up ena ble control the behavior of the pin. note for comm modes 01 or 10 (spi master or spi slave, see table 18-2 on page 46) when configured for spi (spi use = 1 and comm modes [1:0] = spi master or spi slave mode), the input and output direction of pins p1.5, and p1.6 is set automatically by the spi logic. however, pin p1.4's input and output direction is not automatical ly set; it must be explicitly set by firmware. for spi master m ode, pin p1.4 must be configured as an output; for spi slave mode, pin p1.4 must be configured as an input. table 17-11. p1.7 configuration (p17cr) [0x14] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reserved high sink open drain pull-up enable output enable read/write ?r/wr/w? r/w r/w r/w r/w default 0000 0000 this register controls the operation of pin p1.7. the 50 ma sink drive capability is only available in cy7c602xx . in cy7c601xx, only 8 ma sink drive capability is available on this pin regardless of the setting of the high sink bit. the p1.7 gpio?s threshold is always set to ttl. table 17-12. p2 configuration (p2cr) [0x15] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write ?r/wr/wr/w r/w r/w r/w r/w default 0000 0000 in cy7c602xx, this register controls the operation of pins p2.0?p 2.1. in cy7c601xx, this register controls the operation of pin s p2.0?p2.7. the 50-ma sink drive capability is only available on pin p2.7 and only on cy7c601xx. in cy7c602xx, only an 8-ma sink drive capability is available on this pin regardless of the setting of the high sink bit.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 44 of 68 17.2.21 p3 configuration 17.2.22 p4 configuration table 17-13. p3 configuration (p3cr) [0x16] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write ?r/wr/wr/w r/w r/w r/w r/w default 0000 0000 in cy7c602xx, this register controls the operation of pins p3.0?p 3.1. in cy7c601xx, this register controls the operation of pin s p3.0?p3.7. the 50-ma sink drive capability is only available on pin p3.7 and only on cy7c601xx. in cy7c602xx, only an 8-ma sink drive capability is available on this pin regardless of the setting of the high sink bit. table 17-14. p4 configuration (p4cr) [0x17] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register exists only in cy7c601xx. this register controls the operation of pins p4.0?p4.3.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 45 of 68 18. serial peripheral interface (spi) the spi master and slave interface core logic runs on the spi clock domain. the spi clock is a divider off of the cpuclk when i n the master mode. spi is a four pin serial interface comprised of a clock, an enable, and two data pins. figure 18-1. spi block diagram spi state machine ss_n data (8 bit) load empty data (8 bit) load full sclk output enable slave select output enable master in, slave out oe master out, slave in, oe shift buffer input shift buffer output shift buffer sck clock generation sck clock select sck clock phase/polarity select register block sck speed sel master/slave sel sck polarity sck phase little endian sel miso/mosi crossbar gpio block ss_n le_sel sck le_sel sck_oe ss_n_oe miso_oe mosi_oe sck sck_oe ss_n_oe sck ss_n master/slave set miso mosi miso_oe mosi_oe
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 46 of 68 18.1 spi data register when an interrupt occurs to indicate to firmware that a byte of receive data is available or the transmitter holding register i s empty, firmware has seven spi clocks to manage the buffers?to empty th e receiver buffer or to refill the transmit holding register. fa ilure to meet this timing requirement results in incorrect data transfer. 18.2 spi configure register table 18-1. spi data register (spidata) [0x3c] [r/w] bit # 7 6 5 4 3 2 1 0 field spidata[7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when read, this register returns the contents of the receive buffer. when written, it loads the transmit holding register. bit [7:0]: spi data [7:0] table 18-2. spi configure register (spicr) [0x3d] [r/w] bit # 7 6 5 4 3 2 1 0 field swap lsb first comm mode cpol cpha sclk select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: swap 0 = swap function disabled 1 = the spi block swaps its use of smosi and smiso. among other things, this is useful to implement single wire communi- cations similar to spi. bit 6: lsb first 0 = the spi transmits and receives the msb (most significant bit) first. 1 = the spi transmits and receives the lsb (least significant bit) first. bit [5:4]: comm mode [1:0] 0 0: all spi communication disabled 0 1: spi master mode 1 0: spi slave mode 1 1: reserved bit 3: cpol this bit controls the spi clock (sclk) idle polarity. 0 = sclk idles low 1 = sclk idles high bit 2: cpha the clock phase bit controls the phase of the clock on which data is sampled. table 18-3 on page 47 shows the timing for various combinations of lsb first, cpol, and cpha. bit [1:0]: sclk select this field selects the speed of the master sclk. when in master mode, sclk is generated by dividing the base cpuclk important note for comm modes 01b or 10b (spi master or spi slave) when configured for spi, (spi use = 1 ? table 17-10 on page 43), the input and output direction of pins p1.3, p1.5, and p1.6 is set automatically by the spi logic. however, pin p1.4's input and output direction is not automatically set; it must be expl ic- itly set by firmware. for spi master mode, pin p1.4 is configur ed as an output; for spi slave mode, pin p1.4 is configured as an input.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 47 of 68 table 18-3. spi mode timing vs. lsb first, cpol, and cpha lsb first cpha cpol diagram 000 001 010 011 100 101 110 111 sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2bit 3bit 4bit 5bit 6bit 7 lsb sclk ssel data x msb x bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 48 of 68 18.3 spi interface pins the spi interface uses the p1.3?p1.6 pins. these pins ar e configured using the p1.3 and p1.4?p1.6 configuration. 19. timer registers all timer functions of the encore ii lv are provided by a single -timer block. the timer block is asynchronous from the cpu cloc k. the 16-bit free-running counter is used as the time base for ti mer captures and also as a general time base by software. 19.1 registers 19.1.1 free-running counter the 16-bit free-running counter is clocked by the timer capture clock (tcapclk). it is read in software for use as a general-pu rpose time base. when reading the low-order byte, the high-order byte is registered. reading th e high-order byte r eads this register allowing the cpu to read the 16-bit value atomically (loads all bits at one time). the free-running timer generates an interrupt at 1024 ? s rate when clocked by a 4-mhz source. it also generates an interrupt when the free-running counter overflow occurs ? every 16.384 ms (with a 4-mhz source). this extends the length of the timer. figure 19-1. 16-bit free-running counter block diagram table 18-4. spi sclk frequency sclk select cpuclk divisor sclk frequency when cpuclk = 12 mhz 00 6 2 mhz 01 12 1 mhz 10 48 250 khz 11 96 125 khz timer capture clock 16-bit free running counter overflow interrupt/wrap interrupt 1024 s timer interrupt table 19-1. free-running timer low- order byte (frtmrl) [0x20] [r/w] bit # 7 6 5 4 3 2 1 0 field free-running timer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: free-running timer [7:0] this register holds the low-order byte of the 16-bit free-running timer. reading this register moves the high-order byte into a holding register allowing an automatic read of all 16 bits simultaneously. for reads, the actual read occu rs in the cycle when the lo w-order is read. for writes, the act ual time the write occurs is the cycle when the high-order is written. when reading the free-running timer, the lo w-order byte is read first and the high-or der second. when writing, the low-order by te is written first then the high-order byte.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 49 of 68 19.1.2 time capture encore ii lv has two 8-bit captures. each capture has a separate register for rising and falling time. the two 8-bit captures c an be configured as a single 16-bit capture. when configured in this way, the capture 1 registers hold the high-order byte of the 16- bit timer capture value. each of the four capture registers can be programmed to generate an interrupt when it is loaded. figure 19-2. time capture block diagram table 19-2. free-running timer high-order byte (frtmrh) [0x21] [r/w] bit # 7 6 5 4 3 2 1 0 field free-running timer [15:8] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: free-running timer [15:8] when reading the free-running timer, the lo w-order byte is read first and the high-or der second. when writing, the low-order by te is written first, then the high-order byte. table 19-1. timer configur ation (tmrcr) [0x2a] [r/w] bit # 7 6 5 4 3 2 1 0 field first edge hold 8-bit capture prescale [2:0] cap0 16-bit enable reserved read/write r/w r/w r/w r/w r/w ? ? ? default 0 0 0 0 00 0 0 bit 7: first edge hold the first edge hold function applies to all four capture timers. 0 = the time of the most recent edge is held in the capture timer data register. if multiple edges have occurred since reading the capture timer, the time for the most recent one is read. 1 = the time of the first occurrence of an edge is held in t he capture timer data register until the data is read. subsequent e dges are ignored until the capture timer data register is read. bit [6:4]: 8-bit capture prescale [2:0] this field controls which eight bits of the 16 free-running timer are captured when in bit mode. 0 0 0 = capture timer[7:0] 0 0 1 = capture timer[8:1] 0 1 0 = capture timer[9:2] 0 1 1 = capture timer[10:3] 1 0 0 = capture timer[11:4] 1 0 1 = capture timer[12:5] 1 1 0 = capture timer[13:6] 1 1 1 = capture timer[14:7] bit 3: cap0 16-bit enable 0 = capture 0 16-bit mode is disabled 1 = capture 0 16-bit mode is enabled. capture 1 is disabled and the capture 1 rising and falling regi sters are used as an exten sion to the capture 0 registers?extending them to 16 bits. bit [2:0]: reserved source control and configuration external clock internal 24-mhz oscillator internal low power 32-khz oscillator timer capture clock output (4-mhz default) programmable interval timer 16-bit free running counter
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 50 of 68 table 19-2. capture interrupt enable (tcapinte) [0x2b] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved cap1 fall enable cap1 rise enable cap0 fall enable cap0 rise enable read/write ???? r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:4]: reserved bit 3: cap1 fall enable 0 = disable the capture 1 falling edge interrupt 1 = enable the capture 1 falling edge interrupt bit 2: cap1 rise enable 0 = disable the capture 1 rising edge interrupt 1 = enable the capture 1 rising edge interrupt bit 1: cap0 fall enable 0 = disable the capture 0 falling edge interrupt 1 = enable the capture 0 falling edge interrupt bit 0: cap0 rise enable 0 = disable the capture 0 rising edge interrupt 1 = enable the capture 0 rising edge interrupt table 19-3. timer capture 0 rising (tcap0r) [0x22] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 0 rising [7:0] read/write r r r r rr r r default 0 0 0 0 00 0 0 bit [7:0]: capture 0 rising [7:0] this register holds the value of the free-running timer when the last rising edge occurred on the tio0 input. when capture 0 is in 8-bit mode, the bits that are stored here are selected by the prescale [2:0] bits in the timer configuration register. when capture 0 is in 16-bit mode this register holds the lower order eight bits of the 16-bit timer. table 19-4. timer capture 1 rising (tcap1r) [0x23] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 1 rising [7:0] read/write r r r r rr r r default 0 0 0 0 00 0 0 bit [7:0]: capture 1 rising [7:0] this register holds the value of the free-running timer when the last rising edge occurred on the tio1 input. the bits that are stored here are selected by the prescale [2:0] bits in the time r configuration register. when capture 0 is in 16-bit mode this register holds the high-order eight bits of the 16-bit timer from the last tio0 rising edge. table 19-5. timer capture 0 falling (tcap0f) [0x24] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 0 falling [7:0] read/write r r r r rr r r default 0 0 0 0 00 0 0 bit [7:0]: capture 0 falling [7:0] this register holds the value of the free-running timer when the last falling edge occurred on the tio0 input. when capture 0 i s in 8-bit mode, the bits that are stored here are selected by the prescale [2:0] bits in the timer configuration register. when capture 0 is in 16-bit mode this register holds the lower order eight bits of the 16-bit timer.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 51 of 68 ? 19.1.3 programmable interval timer table 19-6. timer capture 1 falling (tcap1f) [0x25] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 1 falling [7:0] read/write r r r r rr r r default 0 0 0 0 00 0 0 bit [7:0]: capture 1 falling [7:0] this register holds the value of the free-running timer when the last falling edge occurred on the tio1 input. the bits stored here are selected by the prescale [2:0] bits in the timer configuration register. when capture 0 is in 16-bit mode this register hol ds the high-order eight bits of the 16-bit timer from the last tio0 falling edge. table 19-7. capture interrupt status (tcapints) [0x2c] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved cap1 fall active cap1 rise active cap0 fall active cap0 rise active read/write ???? r/w r/w r/w r/w default 0 0 0 0 00 0 0 these four bits contains the status bits for the four timer captures for the four timer block capture interrupt sources. writin g any of these bits with 1 clears that interrupt. bit [7:4]: reserved bit 3: cap1 fall active 0 = no event 1 = a falling edge has occurred on tio1 bit 2: cap1 rise active 0 = no event 1 = a rising edge has occurred on tio1 bit 1: cap0 fall active 0 = no event 1 = a falling edge has occurred on tio0 bit 0: cap0 rise active 0 = no event 1 = a rising edge has occurred on tio0 note the interrupt status bits are cleared by firmware to enable su bsequent interrupts. this is achieved by writing a ?1? to the corresponding interrupt status bit. table 19-8. programmable interval timer low (pitmrl) [0x26] [r] bit # 7 6 5 4 3 2 1 0 field prog interval timer [7:0] read/write r r r r rr r r default 0 0 0 0 00 0 0 bit [7:0]: prog interval timer [7:0] this register holds the low-order byte of the 12-bit programmable interval timer. reading this register moves the high-order by te into a holding register allowing an automatic read of all 12 bits simultaneously.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 52 of 68 i table 19-9. programmable interval timer high (pitmrh) [0x27] [r] bit # 7 6 5 4 3 2 1 0 field reserved prog interval timer [11:8] read/write -- -- -- -- rr r r default 0 0 0 0 00 0 0 bit [7:4]: reserved bit [3:0]: prog internal timer [11:8] this register holds the high-order nibble of the 12-bit programma ble interval timer. reading this register returns the high-ord er nibble of the 12-bit timer at the instant when the low-order byte was last read. table 19-10. programmable interval reload low (pirl) [0x28] [r/w] bit # 7 6 5 4 3 2 1 0 field prog interval [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: prog interval [7:0] this register holds the lower eight bits of the timer. when writ ing into the 12-bit reload register, write lower byte first the n the higher nibble. table 19-11. programmable interval reload high (pirh) [0x29] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved prog interval[11:8] read/write -- -- -- -- r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:4]: reserved bit [3:0]: prog interval [11:8] this register holds the higher 4 bits of the timer. when writin g into the 12-bit reload register, write lower byte first then t he higher nibble.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 53 of 68 figure 19-3. timer functional sequence diagram
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 54 of 68 figure 19-4. 16-bit free-running counter loading timing diagram figure 19-5. memory mapped registers read and write timing diagram clk_sys write valid addr write data frt reload ready clk timer 12b prog timer 12b reload interrupt capture timer clk 16b free running counter load 16b free running counter 00a0 00a1 00a2 00a3 00a4 00a5 00a6 00a7 00a8 00a9 00ab 00ac 00ad 00ae 00af 00b0 00b1 00b2 acbe acbf acc0 16-bit free running counter loading timing 12-bit programmable timer load timing memory mapped registers read/write timing diagram clk_sys rd_wrn valid addr rdata wdata
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 55 of 68 20. interrupt controller the interrupt controller and its associated registers allow the user?s code to respond to an interrupt from almost every functi onal block in the encore ii lv devices. the registers associated with th e interrupt controller are disabled either globally or individuall y. the registers also provide a mechanism for users to clear all pending and posted interrupts or clear individual posted or pending i nterrupts. table 20-1 lists all interrupts and the priorities that are available in the encore ii lv devices. table 20-1. interrupt priorities, address, and name interrupt priority interrupt address name 0 0000h reset 1 0004h por/lvd 2 0008h int0 3 000ch spi transmitter empty 4 0010h spi receiver full 5 0014h gpio port 0 6 0018h gpio port 1 7001chint1 8 0020h reserved 9 0024h reserved 10 0028h reserved 11 002ch reserved 12 0030h reserved 13 0034h 1 ms interval timer 14 0038h programmable interval timer 15 003ch timer capture 0 16 0040h timer capture 1 17 0044h 16-bit free-running timer wrap 18 0048h int2 19 004ch reserved 20 0050h gpio port 2 21 0054h gpio port 3 22 0058h gpio port 4 23 005ch reserved 24 0060h reserved 25 0064h sleep timer
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 56 of 68 20.1 architectural description an interrupt is posted when its interrupt conditions occur. this results in the flip-flop in figure 20-1 clocking in a ?1?. the interrupt remains posted until the interrupt is taken or until it is cleared by writing to the appropriate int_clrx register. a posted interrupt is not pending unless it is enabled by setting its interrupt mask bit (in the appropriate int_mskx register). all pending interrupts are processed by the priority encoder to determine the highest priority interrupt which is taken by the m8c if the global interrupt enable bit is set in the cpu_f register. disabling an interrupt by clearing its interrupt mask bit (in the int_mskx register) does not clear a posted interrupt, nor does it prevent an interrupt from bei ng posted. it simply prevents a posted interrupt from becoming pending. nested interrupts are accomplished by reenabling interrupts inside an interrupt service routine. to do this, set the ie bit in the flag register. a block diagram of the encore ii lv interrupt controller is shown in figure 20-1 . figure 20-1. interrupt controller block diagram 20.2 interrupt processing the sequence of events that occur during interrupt processing is as follows: 1. an interrupt becomes active, either because: a. the interrupt condition occurs (for example, a timer expires). b. a previously posted interrupt is enabled through an update of an interrupt mask register. c. an interrupt is pending and gie is set from 0 to 1 in the cpu flag register. 1. the current executing instruction finishes. 2. the internal interru pt is dispatched, taking 13 cycles. during this time, the following actions occur: a. the msb and lsb of program counter and flag registers (cpu_pc and cpu_f) are stored onto the program stack by an automatic call inst ruction (13 cycles) generated during the interrupt acknowledge process. b. the pch, pcl, and flag register (cpu_f) are stored onto the program stack (in that order) by an automatic call instruction (13 cycles) generated during the interrupt acknowledge process. c. the cpu_f register is then cleared. because this clears the gie bit to 0, additional interrupts are temporarily disabled. d. the pch (pc[15:8]) is cleared to zero. e. the interrupt vector is read from the interrupt controller and its value placed into pcl (pc[7:0]). this sets the program counter to point to the appropriate address in the interrupt table (for example, 0004h for the por and lvd interrupt). 1. program execution vectors to the interrupt table. typically, a ljmp instruction in the interrupt table sends execution to the user's interrupt service rout ine (isr) for this interrupt. 2. the isr executes. note that interrupts are disabled because gie =0. in the isr, interrupts are re-enabled if desired, by setting gie = 1 (avoid stack overflow). 3. the isr ends with a reti instruction, which restores the program counter and flag r egisters (cpu_pc and cpu_f). the restored flag register re-enables interrupts, because gie = 1 again. 4. execution resumes at the next instruction, after the one that occurred before the interrupt. however, if there are more pending interrupts, the subsequent interrupts are processed before the next normal program instruction. 20.3 interrupt latency the time between the assertion of an enabled interrupt and the start of its isr is calculated from the following equation. latency = time for current instructio n to finish + time for internal interrupt routine to execute + time for ljmp instruction in interrupt table to execute. for example, if the 5-cycle jmp in struction is ex ecuting when an interrupt becomes active, the to tal number of cpu clock cycles before the isr begins is as follows: (1 to 5 cycles for jmp to finish) + (13 cycles for interrupt routine) + (7 cycles for ljmp) = 21 to 25 cycles. in the example above, at 12 mhz, 25 clock cycles take 2.08 s. interrupt source (timer, gpio, etc.) interrupt tak en or posted interrupt pending interrupt gie interrupt vector mask bit setting d r q 1 priority encoder m8c c o r e interrupt request ... int_mskx int_clrx write cpu_f[0] ...
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 57 of 68 20.4 interrupt registers 20.4.1 interrupt clear register the interrupt clear registers (int_clrx) are used to enable the individual interrupt sources? ability to clear posted interrupt s. when an int_clrx register is read, any bits that are set indi cates an interrupt has been posted for that hardware resource. the refore, reading these registers enables the user to determine all posted interrupts. table 20-1. interrupt clear 0 (int_clr0) [0xda] [r/w] bit # 7 6 5 4 3 2 1 0 field gpio port 1 sleep timer int1 gpio port 0 spi receive spi transmit int0 por/lvd read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when reading this register, 0 = there is no posted interrupt for the corresponding hardware. 1 = there is a posted interrupt for the corresponding hardware. writing a ?0? to the bits clears the posted interrupts for the corresponding hardware. writing a ?1? to the bits and to the ens wint (bit 7 of the int_msk3 register) posts the corresponding hardware interrupt. the gpio interrupts are edge-triggered. table 20-2. interrupt clear 1 (int_clr1) [0xdb] [r/w] bit # 7 6 5 4 3 2 1 0 field tcap0 prog interval timer 1-ms program- mable interrupt reserved read/write r/w r/w r/w ? ?? ? ? default 0 0 0 0 00 0 0 when reading this register, 0 = there is no posted interrupt for the corresponding hardware. 1 = there is a posted interrupt for the corresponding hardware. writing a ?0? to the bits clears the posted interrupts for the corresponding hardware. writing a ?1? to the bits and to the ens wint (bit 7 of the int_msk3 register) posts the corresponding hardware interrupt. table 20-3. interrupt clear 2 (int_clr2) [0xdc] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved gpio port 4 gpio port 3 gpio port 2 reserved int2 16-bit counter wrap tcap1 read/write ? r/w r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 when reading this register, 0 = there is no posted interrupt for the corresponding hardware. 1 = there is a posted interrupt for the corresponding hardware. writing a ?0? to the bits clears the posted interrupts for the corresponding hardware. writing a ?1? to the bits and to the ens wint (bit 7 of the int_msk3 register) posts the corresponding hardware interrupt.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 58 of 68 20.4.2 interrupt mask registers the interrupt mask registers (int_mskx) enable the individual interrupt sources? ability to create pending interrupts. there are four interrupt mask registers (int_msk0, int_msk1, int_msk2, and int_msk3) which are referred to in general as int_mskx. if cleared, each bit in an int_mskx register prevents a posted interrupt from becoming a pending interrupt (input to the priority encoder). however, an interrupt can still post even if its mask bit is zero. all int_mskx bits are independent of all other int_mskx bits. if an int_mskx bit is set, the interrupt source associated with that mask bit generates an interrupt that becomes a pending interrupt. the enable software interrupt (enswint) bit in int_msk3[7] determines the way an individual bit value written to an int_clrx register is interpreted. when cleared, writing 1s to an int_clrx register has no effect. however, writing 0s to an int_clrx register, when enswint is cleared, causes the corresponding interrupt to clear. if the enswint bit is set, 0s written to the int_clrx registers are ignored. however, 1s written to an int_clrx register, when enswint is set, causes an interrupt to post for the corresponding interrupt. software interrupts aid in debugging interrupt service routines by eliminating the ne ed to create system level interactions that are sometimes necessary to create a hardware only interrupt. table 20-4. interrupt mask 3 (int_msk3) [0xde] [r/w] bit # 7 6 5 4 3 2 1 0 field enswint reserved read/write r ? ? ? ? ? ? ? default 0 0 0 0 00 0 0 bit 7: enable software interrupt (enswint) 0= disable. writing 0s to an int_clrx register, when enswint is cleared, clears the corresponding interrupt. 1= enable. writing 1s to an int_clrx register, when enswint is set, posts the corresponding interrupt. bit [6:0]: reserved table 20-5. interrupt mask 2 (int_msk2) [0xdf] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved gpio port 4 int enable gpio port 3 int enable gpio port 2 int enable reserved int2 int enable 16-bit counter wrap int enable tcap1 int enable read/write ? r/w r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: reserved bit 6: gpio port 4 interrupt enable 0 = mask gpio port 4 interrupt 1 = unmask gpio port 4 interrupt bit 5: gpio port 3 interrupt enable 0 = mask gpio port 3 interrupt 1 = unmask gpio port 3 interrupt bit 4: gpio port 2 interrupt enable 0 = mask gpio port 2 interrupt 1 = unmask gpio port 2 interrupt bit 3: reserved bit 2: int2 interrupt enable 0 = mask int2 interrupt 1 = unmask int2 interrupt bit 1: 16-bit counter wrap interrupt enable 0 = mask 16-bit counter wrap interrupt 1 = unmask 16-bit counter wrap interrupt bit 0: tcap1 interrupt enable 0 = mask tcap1 interrupt 1 = unmask tcap1 interrupt the gpio interrupts are edge-triggered.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 59 of 68 20.4.3 interrupt vector clear register table 20-6. interrupt mask 1 (int_msk1) [0xe1] [r/w] bit # 7 6 5 4 3 2 1 0 field tcap0 int enable prog interval timer int enable 1-ms timer int enable reserved read/write r/w r/w r/w ? ?? ? ? default 0 0 0 0 00 0 0 bit 7: tcap0 interrupt enable 0 = mask tcap0 interrupt 1 = unmask tc ap0 interrupt bit 6: prog interval timer interrupt enable 0 = mask prog interval timer interrupt 1 = unmask prog interval timer interrupt bit 5: 1 ms timer interrupt enable 0 = mask 1 ms interrupt 1 = unmask 1 ms interrupt bit [4:0]: reserved table 20-7. interrupt mask 0 (int_msk0) [0xe0] [r/w] bit # 7 6 5 4 3 2 1 0 field gpio port 1 int enable sleep timer int enable int1 int enable gpio port 0 int enable spi receive int enable spi transmit int enable int0 int enable por/lvd int enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: gpio port 1 interrupt enable 0 = mask gpio port 1 interrupt 1 = unmask gpio port 1 interrupt bit 6: sleep timer interrupt enable 0 = mask sleep timer interrupt 1 = unmask sleep timer interrupt bit 5: int1 interrupt enable 0 = mask int1 interrupt 1 = unmask int1 interrupt bit 4: gpio port 0 interrupt enable 0 = mask gpio port 0 interrupt 1 = unmask gpio port 0 interrupt bit 3: spi receive interrupt enable 0 = mask spi receive interrupt 1 = unmask spi receive interrupt bit 2: spi transmit enable 0 = mask spi tr ansmit interrupt 1 = unmask spi transmit interrupt bit 1: int0 interrupt enable 0 = mask int0 interrupt 1 = unmask int0 interrupt bit 0: por/lvd interrupt enable 0 = mask por/lvd interrupt 1 = unmask por/lvd interrupt table 20-8. interrupt vector clear register (int_vc) [0xe2] [r/w] bit # 7 6 5 4 3 2 1 0 field pending interrupt [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 the interrupt vector clear register (int_vc) holds the interrupt vector for the highest priority pending interrupt when read, a nd when written clears all pending interrupts. bit [7:0]: pending interrupt [7:0] 8-bit data value holds the interrupt vector for the highest priority pend ing interrupt. writing to this register clears all pen ding interrupts.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 60 of 68 21. absolute maximum ratings storage temperature ................................ ?40 c to +90 c ambient temperature with power applied .. ?0 c to +70 c supply voltage on v cc relative to v ss ..........?0.5 v to +7.0 v dc input voltage .............................. ?0.5 v to + v cc + 0.5 v dc voltage applied to outputs in high-z state...................................... ?0.5 v to + v cc + 0.5 v maximum total sink output current into port 0 and 1 and pins ............................................................. 70 ma maximum total source output current into gpio pins ............................................................. 30 ma maximum on-chip power dissipation on any gpio pin ......................................................... 50 mw power dissipation .................................................... 300 mw static discharge voltage ............................................. 2200 v latch-up current ...................................................... 200 ma note 4. available only on cy7c601xx p2.7, p3.7, p0.0, p0.1; cy7c602xx p1.3, p1.4, p1.5, p1.6, p1.7. 21.1 dc characteristics parameter description conditions min typical max unit general v cc1 operating voltage cpu speed <= 12 mhz 2.7 3.6 v t fp operating temperature flash programming 0 70 c i cc1 v cc operating supply current cpu =12 mhz, v dd = 3.3 v, t = 75 c cpu =12 mhz, v dd = 2.7 v, t = 25 c 4.25 3.25 11 - ma ma i cc2 v cc operating supply current cpu = 6 mhz, v dd = 3.3 v, t = 75 c cpu = 6 mhz, v dd = 3.3 v, t = 25 c 3.15 2.45 9 - ma ma i cc3 v cc operating supply current cpu = 3 mhz, v dd = 2.7 v, t = 25 c 2.0 - ma i sb1 standby current internal and external oscillators, bandgap, flash, cpu clock, timer clock all disabled 10 ? a low-voltage detect v lvd low-voltage detect trip voltage lvdcr [2:0] set to 000 2.681 2.7 v general-purpose i/o interface r up pull-up resistance 4 12 k ? v icr input threshold voltage low, cmos mode low to high edge 40% 65% v cc v icf input threshold voltage low, cmos mode high to low edge 30% 55% v cc v hc input hysteresis voltage, cmos mode high to low edge 3% 10% v cc v ilttl input low-voltage, ttl mode 0.72 v v ihttl input high voltage, ttl mode 1.6 v v ol1 output low-voltage, high drive [4] i ol1 = 50 ma 1.4 v v ol2 output low-voltage, high drive [4] i ol1 = 25 ma 0.4 v v ol3 output low-voltage, low drive i ol2 = 8 ma 0.8 v v oh output high voltage [4] i oh = 2 ma v cc ? 0.5 v
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 61 of 68 figure 21-1. clock timing 21.2 ac characteristics parameter description conditions min typical max unit clock t eclkdc external clock duty cycle 45 55 % t eclk2 external clock frequency 1 24 mhz f imo internal main oscillator (imo) frequency with proper trim values loaded [5] 18.72 26.4 mhz f ilo internal low-power oscillator (ilo) with proper trim values loaded [5] 15.0001 50.0 khz gpio timing t r_gpio output rise time measured between 10 and 90% v dd and vreg with 50 pf load 50 ns t f_gpio output fall time measured between 10 and 90% v dd and vreg with 50 pf load 15 ns spi timing t smck spi master clock rate f cpuclk /6 2 mhz t ssck spi slave clock rate 2.2 mhz t sckh spi clock high time high for cpol = 0, low for cpol = 1 125 ns t sckl spi clock low time low for cpol = 0, high for cpol = 1 125 ns t mdo master data output time [6] sck to data valid ?25 50 ns t mdo1 master data output time, first bit with cpha = 0 time before leading sck edge 100 ns t msu master input data setup time 50 ns t mhd master input data hold time 50 ns t ssu slave input data setup time 50 ns t shd slave input data hold time 50 ns t sdo slave data output time sck to data valid 100 ns t sdo1 slave data output time, first bit with cpha = 0 time after ss low to data valid 100 ns t sss slave select setup time before first sck edge 150 ns t ssh slave select hold time after last sck edge 150 ns clock t cyc t cl t ch notes 5. refer to clocking on page 22 for details on loading proper trim values. 6. in master mode, first bit is available 0.5 spiclk cycl e before master clock edge is available on the sclk pin.
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 62 of 68 figure 21-2. gpio timing diagram figure 21-3. spi master timing, cpha = 1 10% t r_gpio t f_gpio gpio pin output voltage 90% msb t msu lsb t mhd t sckh t mdo ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl msb lsb
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 63 of 68 figure 21-4. spi slave timing, cpha = 1 figure 21-5. spi master timing, cpha = 0 msb t ssu lsb t shd t sckh t sdo ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sss t ssh msb lsb msb t msu lsb t mhd t sckh t mdo1 ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl t mdo lsb msb
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 64 of 68 figure 21-6. spi slave timing, cpha = 0 1 msb t ssu lsb t shd t sckh t sdo1 ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sdo lsb msb t sss t ssh 22. ordering information ordering code flash size (kb) ram size (bytes) package type CY7C60123-PVXC 8 256 48-pin ssop cy7c60123-pxc 8 256 40-pin pdip cy7c60223-sxc 8 256 24-pin soic cy7c60223-qxc 8 256 24-pin qsop 23. package handling some ic packages require baking before they are soldered to a pcb to remove moisture that may have been absorbed after leaving the factory. a label on the packaging has details about actual bake temperature and the minimum bake time to remove this moistu re. the maximum bake time is the aggregate time that the parts are exposed to the bake temperature. exceeding this exposure time ma y degrade device reliability. parameter description min typical max unit t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 65 of 68 24. package diagrams figure 24-1. 24-pin (300-mil) soic s13 figure 24-2. 24-pin qsop o241 51-85025 *e 0.033 0.228 0.150 0.337 0.053 0.004 0.025 0.008 0.016 0.007 0-8 ref. 0.344 0.157 0.244 bsc. 0.012 0.010 0.069 0.034 0.010 seating plane max. dimensions in inches min. pin 1 id 1 12 24 13 0.004 51-85055-*c
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 66 of 68 figure 24-3. 40-pin (600-mil) molded dip p17 figure 24-4. 48-pin shrunk small outline package o48 51-85019-*b dimensions in inches min. max. seating plane 0.090 0.110 0.140 0.160 0.015 0.060 0.015 0.020 0.009 0.012 0.530 0.550 0.155 0.200 0.570 0.625 0.610 0.685 0.065 0.085 2.040 2.070 0.045 0.055 0.115 0.160 3 min. 1 20 21 40 51-85061-*d
cy7c601xx, cy7c602xx document 38-16016 rev. *j page 67 of 68 25. document history page document title: cy7c601xx, cy7c602xx encore ? ii low-voltage microcontroller document number: 38-16016 rev. ecn orig. of change submission date description of change ** 327601 bon see ecn new data sheet *a 400134 bha see ecn updated power consumption values corrected pin assignment table for 24 qsop, 24 pdip and 28 ssop packages minor text changes for clarification purposes corrected int_msk0 and int_msk1 register address corrected register bit definitions corrected protection mode settings in table 10-7 updated lvd trip point values added block diagrams for timer functional timing replaced tbd?s with actual values added spi block diagram added timing block diagrams removed cy7c60123 die from figure 5-1 removed cy7c60123-wxc from section 22.0 ordering information updated internal 24 mhz oscillator accuracy information added information on sending/receiving data when using 32 khz oscillator *b 505222 tyj see ecn minor text changes gpio capacitance and timing diagram included method to clear capture interrupt status bit discussed sleep and wakeup sequence documented pit timer registers? r/w cap ability corrected to read only modified free-running counter text in section 17.1.1 *c 524104 kkvtmp see ecn change title from wirele ss encore ii to encore ii low voltage *d 1821746 vgt/fsu/aes a see ecn changed ?high current drive? on gpio pins to ?2 ma source current on all gpio pins?. changed the storage temperature from -40c to 90c in ?absolute maximum ratings? section. added the line ?the gpios interrupts are edge-triggered.? in tables 19-2 and 19-6. made timing changes in table 43. added figure 12-1 (srom table) and text after it. also modified table 12-1 based on figure 12-1 (srom table). changed ?capx? to ?tiox? in tables 18-8 and 18-9. changed ?capturex? to ?tiox? in figure 18-3. *e 2620679 cmcc/pyrs 12/12/08 added package handling information formatted code in clocking section, removed reference to external crystal oscillator in tables 12-2 and 12-4 *f 2761532 dvja 09/09/2009 changed default value of the sleep timer from 00(512 hz) to 01(64 hz) in the osc_cr0 [0x1e0] register. *g 2899862 xut 03/26/10 removed obsolete parts from the ordering information table updated package diagrams *h 2978027 datt 07/12/2010 sunset review; no technical updates. updated content to meet style guide and template requirements. *i 2999570 mlim 08/03/2010 minor change to correct revision in the document footer. *j 3275367 nxz 06/06/2011 removed "cy7c60223 24-pin pdip and cy7c60113 28-pin ssop" from figure 7-1. removed ?28 ssop" and "24 pdip" columns from table 7-1. removed figure 24-2 (24-pin pdip) and figure 24-4 (28-pin ssop) updated description field of p1.0 and p1.1 in table 7-1 on page 5
document 38-16016 rev. *j revised june 6, 2011 page 68 of 68 psoc is a registered trademark and encore is a trademark of cypress semiconductor corporation. all product and company names me ntioned in this document may be the trademarks of their respective holders. cy7c601xx, cy7c602xx ? cypress semiconductor corporation, 2006-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. 26. sales, solutions , and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.com/go/automotive clocks and buffers cyp ress.com/go/clocks interface cypress. com/go/interface lighting and power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical and image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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